https://vlsiwiki.soe.ucsc.edu/api.php?action=feedcontributions&user=128.114.59.176&feedformat=atomVlsiwiki - User contributions [en]2024-03-29T15:55:01ZUser contributionsMediaWiki 1.26.2https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=464VLSI Reading Group2008-04-21T23:09:51Z<p>128.114.59.176: /* Spring 2008 */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Jeren Semendari<br />
* Keven Woo<br />
* Derek C<br />
<br />
==Spring 2008==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 4/7/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. <br />
|-<br />
| 4/7/08<br />
| Sheldon<br />
| Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/8895/28127/01257884.pdf?isnumber=28127&prod=CNF&arnumber=1257884&arSt=+689&ared=+692&arAuthor=Rao%2C+R.M.%3B+Liu%2C+F.%3B+Burns%2C+J.L.%3B+Brown%2C+R.B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits]. ICCAD, 2003, pp 689-697 <br />
|-<br />
| 4/14/08<br />
| <br />
| No class (@ ISPD)<br />
|-<br />
| 4/21/08<br />
| Matt<br />
| Satisfiability (No Paper)<br />
|-<br />
| 4/28/08<br />
| Derek<br />
| Verilog-A & Current Work<br />
|-<br />
| 5/5/08<br />
| -<br />
| Out of Town <br />
|-<br />
| 5/12/08<br />
| Jeff<br />
| TBD<br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/26/08<br />
| Nobody<br />
| No class (Memorial Day)<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
|<br />
|-<br />
| 6/9/08<br />
| ?<br />
| No Class (@ DAC)<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].<br />
<br />
<br />
== Old Schedules ==<br />
=== Winter 2008 ===<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
|<br />
| NO MEETING<br />
|-<br />
| 3/13/08 <br />
| Janak H. Patel (UIUC)<br />
| CMOS Process Variations: A "Critical Operation Point" hypothesis <br />
|-<br />
|}</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Technology_Setup&diff=459Technology Setup2008-04-09T18:51:50Z<p>128.114.59.176: /* Setting up the CAD Tools */</p>
<hr />
<div>== Connecting Remotely ==<br />
<br />
=== From Linux/Unix ===<br />
<br />
First of all, the tools are only set up on lab machines (mosis4.cse.ucsc.edu for CMPE222/223, your specific lab machine in CMPE125 or on any of the mada machines for Jose and my research groups). You must run them remotely on the machines by exporting your X display:<br />
<br />
ssh -Y mosis4.cse.ucsc.edu<br />
<br />
and you must have an X11 client on your computer. You can do this from home if you have a fast internet connection. Otherwise, you must use the computing labs.<br />
<br />
=== From Win32 ===<br />
<br />
To display on a win32 machine (vista), you should do this:<br />
<br />
1. Install xming from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-6-9-0-28-setup.exe<br />
<br />
2. Install Xming fonts from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-fonts-7-3-0-2-setup.exe<br />
<br />
3. Install putty from http://the.earth.li/~sgtatham/putty/latest/x86/putty.exe<br />
<br />
4. Start Xming<br />
<br />
5. start putty (an SSH client)<br />
<br />
6. in the "SSH->Tunnels" page of putty, click on "Enable X forwarding"<br />
<br />
7. In the Session page of putty, write the hostname (mosis4.cse.ucsc.edu). You can also write your username like this username@mosis4.cse.ucsc.edu. Hit "Save" to save the seesion for future use<br />
<br />
9. Hit "Open" to start your session<br />
<br />
icfb should now work OK, and display to your local machine<br />
<br />
== Setting up the CAD Tools ==<br />
<br />
On this machine, all of the CAD tools are set up by a single setup file called /mada/software/setup.sh. It is written for bash, so you will need to run this shell first if you do not already. You can check your shell by typing: <br />
<br />
echo $SHELL<br />
<br />
The setup for CMPE125 is /opt/setup_synopsys.sh so change the name below as appropriate.<br />
<br />
=== Setup with bash ===<br />
<br />
In your .bashrc file add the following lines:<br />
<br />
source /mada/software/setup.sh<br />
<br />
You must now log out and log back in to get the new setup.<br />
<br />
=== Setup with csh or tcsh ===<br />
<br />
If your default shell is cshrc (the SOE default), you can either a) request that the SOE change it via itrequest b) run bash at the end of your .cshrc file or c) use the configuration file that is here:<br />
<br />
/mada/software/setup.csh<br />
<br />
Note, however, that there may be errors in this file and you should contact SOE tech support if there are differences between it and the bash setup.sh file. THIS IS NOT THE RECOMMENDED SETUP.<br />
<br />
You must now log out and log back in to get the new setup.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Technology_Setup&diff=458Technology Setup2008-04-09T18:51:42Z<p>128.114.59.176: </p>
<hr />
<div>== Connecting Remotely ==<br />
<br />
=== From Linux/Unix ===<br />
<br />
First of all, the tools are only set up on lab machines (mosis4.cse.ucsc.edu for CMPE222/223, your specific lab machine in CMPE125 or on any of the mada machines for Jose and my research groups). You must run them remotely on the machines by exporting your X display:<br />
<br />
ssh -Y mosis4.cse.ucsc.edu<br />
<br />
and you must have an X11 client on your computer. You can do this from home if you have a fast internet connection. Otherwise, you must use the computing labs.<br />
<br />
=== From Win32 ===<br />
<br />
To display on a win32 machine (vista), you should do this:<br />
<br />
1. Install xming from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-6-9-0-28-setup.exe<br />
<br />
2. Install Xming fonts from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-fonts-7-3-0-2-setup.exe<br />
<br />
3. Install putty from http://the.earth.li/~sgtatham/putty/latest/x86/putty.exe<br />
<br />
4. Start Xming<br />
<br />
5. start putty (an SSH client)<br />
<br />
6. in the "SSH->Tunnels" page of putty, click on "Enable X forwarding"<br />
<br />
7. In the Session page of putty, write the hostname (mosis4.cse.ucsc.edu). You can also write your username like this username@mosis4.cse.ucsc.edu. Hit "Save" to save the seesion for future use<br />
<br />
9. Hit "Open" to start your session<br />
<br />
icfb should now work OK, and display to your local machine<br />
<br />
== Setting up the CAD Tools ==<br />
<br />
On this machine, all of the CAD tools are set up by a single setup file called /mada/software/setup.sh. It is written for bash, so you will need to run this shell first if you do not already. You can check your shell by typing: <br />
<br />
echo $SHELL<br />
<br />
The setup for CMPE125 is /opt/setup_synopsys.sh so change the name below as appropriate.<br />
<br />
<br />
=== Setup with bash ===<br />
<br />
In your .bashrc file add the following lines:<br />
<br />
source /mada/software/setup.sh<br />
<br />
You must now log out and log back in to get the new setup.<br />
<br />
=== Setup with csh or tcsh ===<br />
<br />
If your default shell is cshrc (the SOE default), you can either a) request that the SOE change it via itrequest b) run bash at the end of your .cshrc file or c) use the configuration file that is here:<br />
<br />
/mada/software/setup.csh<br />
<br />
Note, however, that there may be errors in this file and you should contact SOE tech support if there are differences between it and the bash setup.sh file. THIS IS NOT THE RECOMMENDED SETUP.<br />
<br />
You must now log out and log back in to get the new setup.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Technology_Setup&diff=457Technology Setup2008-04-09T18:50:28Z<p>128.114.59.176: /* From Linux/Unix */</p>
<hr />
<div>== Connecting Remotely ==<br />
<br />
=== From Linux/Unix ===<br />
<br />
First of all, the tools are only set up on lab machines (mosis4.cse.ucsc.edu for CMPE222/223, your specific lab machine in CMPE125 or on any of the mada machines for Jose and my research groups). You must run them remotely on the machines by exporting your X display:<br />
<br />
ssh -Y mosis4.cse.ucsc.edu<br />
<br />
and you must have an X11 client on your computer. You can do this from home if you have a fast internet connection. Otherwise, you must use the computing labs.<br />
<br />
=== From Win32 ===<br />
<br />
To display on a win32 machine (vista), you should do this:<br />
<br />
1. Install xming from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-6-9-0-28-setup.exe<br />
<br />
2. Install Xming fonts from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-fonts-7-3-0-2-setup.exe<br />
<br />
3. Install putty from http://the.earth.li/~sgtatham/putty/latest/x86/putty.exe<br />
<br />
4. Start Xming<br />
<br />
5. start putty (an SSH client)<br />
<br />
6. in the "SSH->Tunnels" page of putty, click on "Enable X forwarding"<br />
<br />
7. In the Session page of putty, write the hostname (mosis4.cse.ucsc.edu). You can also write your username like this username@mosis4.cse.ucsc.edu. Hit "Save" to save the seesion for future use<br />
<br />
9. Hit "Open" to start your session<br />
<br />
icfb should now work OK, and display to your local machine<br />
<br />
== Setting up the CAD Tools ==<br />
<br />
On this machine, all of the CAD tools are set up by a single setup file called /mada/software/setup.sh. It is written for bash, so you will need to run this shell first if you do not already. You can check your shell by typing:<br />
<br />
echo $SHELL<br />
<br />
=== Setup with bash ===<br />
<br />
In your .bashrc file add the following lines:<br />
<br />
source /mada/software/setup.sh<br />
<br />
You must now log out and log back in to get the new setup.<br />
<br />
=== Setup with csh or tcsh ===<br />
<br />
If your default shell is cshrc (the SOE default), you can either a) request that the SOE change it via itrequest b) run bash at the end of your .cshrc file or c) use the configuration file that is here:<br />
<br />
/mada/software/setup.csh<br />
<br />
Note, however, that there may be errors in this file and you should contact SOE tech support if there are differences between it and the bash setup.sh file. THIS IS NOT THE RECOMMENDED SETUP.<br />
<br />
You must now log out and log back in to get the new setup.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Technology_Setup&diff=456Technology Setup2008-04-09T18:49:39Z<p>128.114.59.176: /* From Linux/Unix */</p>
<hr />
<div>== Connecting Remotely ==<br />
<br />
=== From Linux/Unix ===<br />
<br />
First of all, the tools are only set up on mosis4.cse.ucsc.edu (for CMPE 222) or on any of the mada machines (for Jose and my research groups). You must run them remotely on the machines by exporting your X display:<br />
<br />
ssh -Y mosis4.cse.ucsc.edu<br />
<br />
and you must have an X11 client on your computer. You can do this from home if you have a fast internet connection. Otherwise, you must use the computing labs.<br />
<br />
=== From Win32 ===<br />
<br />
To display on a win32 machine (vista), you should do this:<br />
<br />
1. Install xming from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-6-9-0-28-setup.exe<br />
<br />
2. Install Xming fonts from http://sourceforge.net/project/downloading.php?group_id=156984&filename=Xming-fonts-7-3-0-2-setup.exe<br />
<br />
3. Install putty from http://the.earth.li/~sgtatham/putty/latest/x86/putty.exe<br />
<br />
4. Start Xming<br />
<br />
5. start putty (an SSH client)<br />
<br />
6. in the "SSH->Tunnels" page of putty, click on "Enable X forwarding"<br />
<br />
7. In the Session page of putty, write the hostname (mosis4.cse.ucsc.edu). You can also write your username like this username@mosis4.cse.ucsc.edu. Hit "Save" to save the seesion for future use<br />
<br />
9. Hit "Open" to start your session<br />
<br />
icfb should now work OK, and display to your local machine<br />
<br />
== Setting up the CAD Tools ==<br />
<br />
On this machine, all of the CAD tools are set up by a single setup file called /mada/software/setup.sh. It is written for bash, so you will need to run this shell first if you do not already. You can check your shell by typing:<br />
<br />
echo $SHELL<br />
<br />
=== Setup with bash ===<br />
<br />
In your .bashrc file add the following lines:<br />
<br />
source /mada/software/setup.sh<br />
<br />
You must now log out and log back in to get the new setup.<br />
<br />
=== Setup with csh or tcsh ===<br />
<br />
If your default shell is cshrc (the SOE default), you can either a) request that the SOE change it via itrequest b) run bash at the end of your .cshrc file or c) use the configuration file that is here:<br />
<br />
/mada/software/setup.csh<br />
<br />
Note, however, that there may be errors in this file and you should contact SOE tech support if there are differences between it and the bash setup.sh file. THIS IS NOT THE RECOMMENDED SETUP.<br />
<br />
You must now log out and log back in to get the new setup.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=454VLSI Reading Group2008-04-07T23:52:04Z<p>128.114.59.176: /* Spring 2008 */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Jeren Semendari<br />
* Keven Woo<br />
* Derek C<br />
<br />
==Spring 2008==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 4/7/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. <br />
|-<br />
| 4/7/08<br />
| Sheldon<br />
| Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/8895/28127/01257884.pdf?isnumber=28127&prod=CNF&arnumber=1257884&arSt=+689&ared=+692&arAuthor=Rao%2C+R.M.%3B+Liu%2C+F.%3B+Burns%2C+J.L.%3B+Brown%2C+R.B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits]. ICCAD, 2003, pp 689-697 <br />
|-<br />
| 4/14/08<br />
| <br />
| No class (@ ISPD)<br />
|-<br />
| 4/21/08<br />
| Matt<br />
| Satisfiability (No Paper)<br />
|-<br />
| 4/21/08<br />
| ?<br />
| TBD<br />
|-<br />
| 4/28/08<br />
| ?<br />
| TBD<br />
|-<br />
| 4/28/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/5/08<br />
| <br />
| No Class (@ DAC) <br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/26/08<br />
| Nobody<br />
| No class (Memorial Day)<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].<br />
<br />
<br />
== Old Schedules ==<br />
=== Winter 2008 ===<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
|<br />
| NO MEETING<br />
|-<br />
| 3/13/08 <br />
| Janak H. Patel (UIUC)<br />
| CMOS Process Variations: A "Critical Operation Point" hypothesis <br />
|-<br />
|}</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=453VLSI Reading Group2008-04-07T23:51:28Z<p>128.114.59.176: /* Spring 2008 */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Jeren Semendari<br />
* Keven Woo<br />
* Derek C<br />
<br />
==Spring 2008==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 4/7/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. <br />
|-<br />
| 4/7/08<br />
| Sheldon<br />
| Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/8895/28127/01257884.pdf?isnumber=28127&prod=CNF&arnumber=1257884&arSt=+689&ared=+692&arAuthor=Rao%2C+R.M.%3B+Liu%2C+F.%3B+Burns%2C+J.L.%3B+Brown%2C+R.B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits]. ICCAD, 2003, pp 689-697 <br />
|-<br />
| 4/14/08<br />
| <br />
| No class (@ ISPD)<br />
|-<br />
| 4/21/08<br />
| Matt<br />
| Satisfiability (No Paper)<br />
|-<br />
| 4/21/08<br />
| ?<br />
| TBD<br />
|-<br />
| 4/28/08<br />
| ?<br />
| TBD<br />
|-<br />
| 4/28/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/5/08<br />
| Nobody<br />
| Out of Town <br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/26/08<br />
| Nobody<br />
| No class (Memorial Day)<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].<br />
<br />
<br />
== Old Schedules ==<br />
=== Winter 2008 ===<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
|<br />
| NO MEETING<br />
|-<br />
| 3/13/08 <br />
| Janak H. Patel (UIUC)<br />
| CMOS Process Variations: A "Critical Operation Point" hypothesis <br />
|-<br />
|}</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=452VLSI Reading Group2008-04-07T23:43:44Z<p>128.114.59.176: /* Spring 2008 */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Jeren Semendari<br />
* Keven Woo<br />
* Derek C<br />
<br />
==Spring 2008==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 4/7/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. <br />
|-<br />
| 4/7/08<br />
| Sheldon<br />
| Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/8895/28127/01257884.pdf?isnumber=28127&prod=CNF&arnumber=1257884&arSt=+689&ared=+692&arAuthor=Rao%2C+R.M.%3B+Liu%2C+F.%3B+Burns%2C+J.L.%3B+Brown%2C+R.B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits]. ICCAD, 2003, pp 689-697 <br />
|-<br />
| 4/14/08<br />
| <br />
| No class (@ ISPD)<br />
|-<br />
| 4/21/08<br />
| Matt<br />
| Satisfiability<br />
|-<br />
| 4/21/08<br />
| ?<br />
| TBD<br />
|-<br />
| 4/28/08<br />
| ?<br />
| TBD<br />
|-<br />
| 4/28/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/5/08<br />
| Nobody<br />
| Out of Town <br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/12/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/19/08<br />
| ?<br />
| TBD<br />
|-<br />
| 5/26/08<br />
| Nobody<br />
| No class (Memorial Day)<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
|-<br />
| 6/2/08<br />
| ?<br />
| TBD<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].<br />
<br />
<br />
== Old Schedules ==<br />
=== Winter 2008 ===<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
|<br />
| NO MEETING<br />
|-<br />
| 3/13/08 <br />
| Janak H. Patel (UIUC)<br />
| CMOS Process Variations: A "Critical Operation Point" hypothesis <br />
|-<br />
|}</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=437VLSI Reading Group2008-03-31T17:41:49Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Spring 2008 Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
<br />
==Spring 2008 Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 4/3/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. <br />
|-<br />
| 4/3/08<br />
| Sheldon<br />
| TBD <br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].<br />
<br />
<br />
==Winter 2008 Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
|<br />
| NO MEETING<br />
|-<br />
| 3/13/08 <br />
| Janak H. Patel (UIUC)<br />
| CMOS Process Variations: A "Critical Operation Point" hypothesis <br />
|-<br />
|}</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=436VLSI Reading Group2008-03-31T17:39:13Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
* Linh Hoang<br />
<br />
==Winter 2008 Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
|<br />
| NO MEETING<br />
|-<br />
| 3/13/08 <br />
| Janak H. Patel (UIUC)<br />
| CMOS Process Variations: A "Critical Operation Point" hypothesis <br />
|-<br />
|}<br />
<br />
==Spring 2008 Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 4/3/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. <br />
|-<br />
| 4/3/08<br />
| Sheldon<br />
| TBD <br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=412VLSI Reading Group2008-03-03T21:51:34Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
* Linh Hoang<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.<br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
| Rigo<br />
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.<br />
328-333. <br />
|-<br />
| 3/6/08<br />
| Sheldon<br />
| TBD <br />
|-<br />
| 3/13/08 1-2pm<br />
| Janak H. Patel (UIUC)<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=407VLSI Reading Group2008-02-21T21:29:40Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
* Linh Hoang<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti] <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Something on thermal modeling... <br />
|-<br />
| 2/28/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.<br />
|-<br />
| 3/6/08<br />
| Rigo?<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=386VLSI Reading Group2008-02-12T16:25:21Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
* Linh Hoang<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Linh<br />
| Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457. <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Something on thermal modeling... <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=380VLSI Reading Group2008-02-05T21:29:13Z<p>128.114.59.176: /* Participants */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
* Linh Hoang<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Something on thermal modeling... <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Main_Page&diff=378Main Page2008-02-05T21:19:16Z<p>128.114.59.176: </p>
<hr />
<div>=== [[Technology Setup]] ===<br />
This descsribes how to configure the software on the MOSIS cluster (e.g. mosis4) and the private mada cluster to use all CAD tools.<br />
<br />
=== [[Full-Custom Tutorials]] ===<br />
This is a collection of tutorials primarily for [http://www.soe.ucsc.edu/classes/cmpe222/Fall07/ CMPE222]. These emphasize a full-custom chip design flow using the [http://www.eda.ncsu.edu/wiki/NCSU_CDK NCSU CDK] and [http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html MOSIS SCMOS] design rules.<br />
<br />
=== [[Standard-Cell Tutorials]] ===<br />
This is a collection of tutorials primarily for [http://www.soe.ucsc.edu/classes/cmpe223/Winter08 CMPE223]. These emphasize a standard-cell chip design flow using the Oaklahoma State cell library.<br />
<br />
=== [[VLSI/Design Automation Group]] ===<br />
Prof. Matthew Guthaus' research group.<br />
<br />
=== [[Paper/Thesis Guide]] ===<br />
Some useful information on how I recommend to write/edit papers.<br />
<br />
=== [[VLSI Reading Group]] ===<br />
Starting in Winter 2008, there will be a weekly seminar (CMPE 280G) on VLSI and Design Automation. This is where the schedule and possible papers are organized.<br />
<br />
<br />
Consult the [http://meta.wikimedia.org/wiki/Help:Contents User's Guide] for information on using the wiki software.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Hierarchical_Design_and_Floorplanning&diff=377Hierarchical Design and Floorplanning2008-02-05T21:19:05Z<p>128.114.59.176: New page: This is a tutorial on how to do floorplanning, and place and route. Essentially backend design and customization. The front-end synthesize is done with Synopsys Design Compiler and back-e...</p>
<hr />
<div>This is a tutorial on how to do floorplanning, and place and route. Essentially backend design and customization. The front-end synthesize is done with Synopsys Design Compiler and back-end is done with SOC Encounter. Following this tutorial will lead to a final GDSII of your layout. Both utilities are available on mosis4.cse.ucsc.edu or mada*, bacon servers. Coming Soon!</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=376Standard-Cell Tutorials2008-02-05T21:19:02Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR><br />
# [[Advanced Synopsys Design Compiler]]<BR><br />
# [[Simulating Verilog]]<BR><br />
# [[Cadence Encounter]]<BR><br />
# [[Hierarchical Design and Floorplanning]]<br />
<br />
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=375VLSI Reading Group2008-02-05T21:18:04Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| Something on thermal modeling... <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=374VLSI Reading Group2008-02-05T21:17:27Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=373VLSI Reading Group2008-02-05T21:17:03Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 2/07/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=372VLSI Reading Group2008-02-05T21:15:48Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 2/14/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/14/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/21/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/21/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| Mohammed<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Simulating_Verilog&diff=371Simulating Verilog2008-02-05T20:35:18Z<p>128.114.59.176: /* VCS */</p>
<hr />
<div>== Introduction ==<br />
<br />
This section will briefly talk about how to simulate Verilog. You can simulate Verilog that is either behavioral, gate-level, or back-annotated (with delays). Behavioral and gate-level are done in the same way, but back annotate requires an extra system call in your Verilog.<br />
<br />
The first thing I recommend that you do is to create a "project.f" file that is just a list of all of your Verilog files. Like this:<br />
<br />
sram.v<br />
sram_tb.v<br />
<br />
== Running Verilog ==<br />
<br />
You can use three different Verilog simulators: ncverilog ("ncverilog"), VCS ("vcs") or verilog-XL ("verilog"). There is also a 4th GNU simulator called [http://www.icarus.com/eda/verilog/ Icarus Verilog] that you can install on your own computer.<br />
<br />
=== ncverilog ===<br />
<br />
Simply run:<br />
<br />
ncverilog -f project.f<br />
<br />
Look for any warnings or errors. At the end of the output, you should see:<br />
<br />
Simulation complete via $finish(1) at time 10 US + 0<br />
./sram_tb.v:64 $finish();<br />
ncsim> exit<br />
<br />
<br />
If you want to view the outputs in a GUI, you can run:<br />
<br />
ncverilog -f project.f +gui<br />
<br />
This will compile the verilog and run SimVision. There is more on SimVision in the [[Advanced Testbenches]] tutorial.<br />
<br />
You can also put these extra arguments in the project.f file.<br />
<br />
=== VCS ===<br />
<br />
To run VCS:<br />
<br />
vcs +v2k -f project.f<br />
./simv<br />
<br />
Specifying -R on the command line will run it immediately and not produce the simv binary.<br />
<br />
Specifying +gui on the command line will load the SimVision GUI.<br />
<br />
=== Verilog-XL ===<br />
<br />
Verilog-XL does not support much of Verilog 2001. However, given that, it can be run in the same way:<br />
<br />
verilog -f project.f<br />
<br />
or:<br />
<br />
verilog -f project.f +gui<br />
<br />
=== Icarus Verilog ===<br />
<br />
Icarus can be run like this:<br />
<br />
iverilog -c project.f<br />
<br />
Note that this will *compile* the verilog into a binary called "a.out". To actually run the Verilog, you must now run it: <br />
<br />
./a.out<br />
<br />
Icarus Verilog seems to be more lenient on errors in Verilog code. You should make sure it compiles in NCVerilog too. Icarus does not come with a GUI, so you will either need to use the $display command or install [http://home.nc.rr.com/gtkwave/ GTKWave].<br />
<br />
== Simulating Verilog in Ultrasim ==<br />
<br />
For non-digital simulations, you can simulate a structural Verilog netlist in Ultrasim as well. However, you need to supply the spice subcircuits of the library:<br />
<br />
/mada/software/techfiles/osu_soc_v2.7/cadence/lib/tsmc025/signalstorm/osu025_stdcells.sp<br />
<br />
<br />
<br />
== Back-Annotation ==<br />
<br />
In order to back-annotate, you should output an SDF file from either Synopsys Design Compiler (before physical design) or from SoC encounter. Each SDF format is sometimes different, so you may have to hack it to get it to work. Common incompatibilities are the dilimiting characters in hierarchical names, for example. Carefully watch the warnings!<br />
<br />
The system call to back-annotate is like this:<br />
<br />
initial begin<br />
$sdf_annotate("gate/lfsr-final.sdf", l0);<br />
end<br />
<br />
where lfsr.sdf is the SDF file and l0 is the instance name of the top module that you synthesized. Note that you should not be using your unsynthesized verilog now. Use the output from synthesis in the file, gate/lfsr-final.v, along with your original testbench.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Simulating_Verilog&diff=370Simulating Verilog2008-02-05T20:17:35Z<p>128.114.59.176: /* Running Verilog */</p>
<hr />
<div>== Introduction ==<br />
<br />
This section will briefly talk about how to simulate Verilog. You can simulate Verilog that is either behavioral, gate-level, or back-annotated (with delays). Behavioral and gate-level are done in the same way, but back annotate requires an extra system call in your Verilog.<br />
<br />
The first thing I recommend that you do is to create a "project.f" file that is just a list of all of your Verilog files. Like this:<br />
<br />
sram.v<br />
sram_tb.v<br />
<br />
== Running Verilog ==<br />
<br />
You can use three different Verilog simulators: ncverilog ("ncverilog"), VCS ("vcs") or verilog-XL ("verilog"). There is also a 4th GNU simulator called [http://www.icarus.com/eda/verilog/ Icarus Verilog] that you can install on your own computer.<br />
<br />
=== ncverilog ===<br />
<br />
Simply run:<br />
<br />
ncverilog -f project.f<br />
<br />
Look for any warnings or errors. At the end of the output, you should see:<br />
<br />
Simulation complete via $finish(1) at time 10 US + 0<br />
./sram_tb.v:64 $finish();<br />
ncsim> exit<br />
<br />
<br />
If you want to view the outputs in a GUI, you can run:<br />
<br />
ncverilog -f project.f +gui<br />
<br />
This will compile the verilog and run SimVision. There is more on SimVision in the [[Advanced Testbenches]] tutorial.<br />
<br />
You can also put these extra arguments in the project.f file.<br />
<br />
=== VCS ===<br />
<br />
To run VCS:<br />
<br />
vcs +v2k -f project.f<br />
./simv<br />
<br />
Specifying -R on the command line will run it immediately and not produce the simv binary.<br />
<br />
=== Verilog-XL ===<br />
<br />
Verilog-XL does not support much of Verilog 2001. However, given that, it can be run in the same way:<br />
<br />
verilog -f project.f<br />
<br />
or:<br />
<br />
verilog -f project.f +gui<br />
<br />
=== Icarus Verilog ===<br />
<br />
Icarus can be run like this:<br />
<br />
iverilog -c project.f<br />
<br />
Note that this will *compile* the verilog into a binary called "a.out". To actually run the Verilog, you must now run it: <br />
<br />
./a.out<br />
<br />
Icarus Verilog seems to be more lenient on errors in Verilog code. You should make sure it compiles in NCVerilog too. Icarus does not come with a GUI, so you will either need to use the $display command or install [http://home.nc.rr.com/gtkwave/ GTKWave].<br />
<br />
== Simulating Verilog in Ultrasim ==<br />
<br />
For non-digital simulations, you can simulate a structural Verilog netlist in Ultrasim as well. However, you need to supply the spice subcircuits of the library:<br />
<br />
/mada/software/techfiles/osu_soc_v2.7/cadence/lib/tsmc025/signalstorm/osu025_stdcells.sp<br />
<br />
<br />
<br />
== Back-Annotation ==<br />
<br />
In order to back-annotate, you should output an SDF file from either Synopsys Design Compiler (before physical design) or from SoC encounter. Each SDF format is sometimes different, so you may have to hack it to get it to work. Common incompatibilities are the dilimiting characters in hierarchical names, for example. Carefully watch the warnings!<br />
<br />
The system call to back-annotate is like this:<br />
<br />
initial begin<br />
$sdf_annotate("gate/lfsr-final.sdf", l0);<br />
end<br />
<br />
where lfsr.sdf is the SDF file and l0 is the instance name of the top module that you synthesized. Note that you should not be using your unsynthesized verilog now. Use the output from synthesis in the file, gate/lfsr-final.v, along with your original testbench.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Vlsiwiki:About&diff=363Vlsiwiki:About2008-01-31T17:07:41Z<p>128.114.59.176: New page: This is a page for documenting VLSI and CAD information at [http://www.soe.ucsc.edu UCSC Baskin School of Engineering]. It is intended for both class and research use. Only public informat...</p>
<hr />
<div>This is a page for documenting VLSI and CAD information at [http://www.soe.ucsc.edu UCSC Baskin School of Engineering]. It is intended for both class and research use. Only public information is kept on this server.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=360Standard-Cell Tutorials2008-01-31T17:03:58Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR><br />
# [[Advanced Synopsys Design Compiler]]<BR><br />
# [[Simulating Verilog]]<BR><br />
# [[Cadence Encounter]]<BR><br />
<br />
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=359VLSI Reading Group2008-01-31T16:54:00Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/7/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/7/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/14/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/14/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/21/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/21/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=358VLSI Reading Group2008-01-31T16:50:48Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]<br />
* Sheldon Logan<br />
* Keven Woo<br />
* Mohammed Jamil<br />
* J. Semendari<br />
* Yaron Kretchmer<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| Yaron<br />
| Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. <br />
<br />
|-<br />
| 1/31/08<br />
| Rigo<br />
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008. <br />
|-<br />
| 2/7/08<br />
| Sheldon<br />
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003. <br />
|-<br />
| 2/7/08<br />
| Keven<br />
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.<br />
|-<br />
| 2/14/08<br />
| Jeff<br />
| Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830. <br />
|-<br />
| 2/14/08<br />
| Linh<br />
| TBD <br />
|-<br />
| 2/21/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/21/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Potential Papers==<br />
<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.<br />
<br />
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.<br />
<br />
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.<br />
<br />
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Simulating_Verilog&diff=348Simulating Verilog2008-01-28T23:35:45Z<p>128.114.59.176: </p>
<hr />
<div>== Introduction ==<br />
<br />
This section will briefly talk about how to simulate Verilog. You can simulate Verilog that is either behavioral, gate-level, or back-annotated (with delays). Behavioral and gate-level are done in the same way, but back annotate requires an extra system call in your Verilog.<br />
<br />
== Running Verilog ==<br />
<br />
You can use two different Verilog simulators: ncverilog ("ncverilog") or verilog-XL ("verilog"). <br />
<br />
== Simulating Verilog in Ultrasim ==<br />
<br />
For non-digital simulations, you can simulate a structural Verilog netlist in Ultrasim as well. However, you need to supply the spice subcircuits of the library:<br />
<br />
/mada/software/techfiles/osu_soc_v2.7/cadence/lib/tsmc025/signalstorm/osu025_stdcells.sp<br />
<br />
<br />
<br />
== Back-Annotation ==<br />
<br />
In order to back-annotate, you should output an SDF file from either Synopsys Design Compiler (before physical design) or from SoC encounter. Each SDF format is sometimes different, so you may have to hack it to get it to work. Common incompatibilities are the dilimiting characters in hierarchical names, for example. Carefully watch the warnings!<br />
<br />
The system call to back-annotate is like this:<br />
<br />
initial begin<br />
$sdf_annotate("gate/lfsr-final.sdf", l0);<br />
end<br />
<br />
where lfsr.sdf is the SDF file and l0 is the instance name of the top module that you synthesized. Note that you should not be using your unsynthesized verilog now. Use the output from synthesis in the file, gate/lfsr-final.v, along with your original testbench.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Simulating_Verilog&diff=347Simulating Verilog2008-01-28T23:33:19Z<p>128.114.59.176: </p>
<hr />
<div>== Introduction ==<br />
<br />
This section will briefly talk about how to simulate Verilog. You can simulate Verilog that is either behavioral, gate-level, or back-annotated (with delays). Behavioral and gate-level are done in the same way, but back annotate requires an extra system call in your Verilog.<br />
<br />
== Back-Annotation ==<br />
<br />
In order to back-annotate, you should output an SDF file from either Synopsys Design Compiler (before physical design) or from SoC encounter. Each SDF format is sometimes different, so you may have to hack it to get it to work. Common incompatibilities are the dilimiting characters in hierarchical names, for example. Carefully watch the warnings!<br />
<br />
The system call to back-annotate is like this:<br />
<br />
initial begin<br />
$sdf_annotate("gate/lfsr-final.sdf", l0);<br />
end<br />
<br />
where lfsr.sdf is the SDF file and l0 is the instance name of the top module that you synthesized. Note that you should not be using your unsynthesized verilog now. Use the output from synthesis in the file, gate/lfsr-final.v, along with your original testbench.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Simulating_Verilog&diff=346Simulating Verilog2008-01-28T21:56:47Z<p>128.114.59.176: New page: == Introduction == This section will talk about how to simulate Verilog.</p>
<hr />
<div>== Introduction ==<br />
<br />
This section will talk about how to simulate Verilog.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=345Standard-Cell Tutorials2008-01-28T21:56:15Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR><br />
# [[Simulating Verilog]]<BR><br />
# [[Cadence Encounter]]<BR><br />
<br />
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Main_Page&diff=327Main Page2008-01-15T21:46:20Z<p>128.114.59.176: /* Standard-Cell Tutorials */</p>
<hr />
<div>=== [[Technology Setup]] ===<br />
This descsribes how to configure the software on the MOSIS cluster (e.g. mosis4) and the private mada cluster to use all CAD tools.<br />
<br />
=== [[Full-Custom Tutorials]] ===<br />
This is a collection of tutorials primarily for [http://www.soe.ucsc.edu/classes/cmpe222/Fall07/ CMPE222]. These emphasize a full-custom chip design flow using the [http://www.eda.ncsu.edu/wiki/NCSU_CDK NCSU CDK] and [http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html MOSIS SCMOS] design rules.<br />
<br />
=== [[Standard-Cell Tutorials]] ===<br />
This is a collection of tutorials primarily for [http://www.soe.ucsc.edu/classes/cmpe223/Winter08 CMPE223]. These emphasize a standard-cell chip design flow using the Oaklahoma State cell library.<br />
<br />
=== [[VLSI/Design Automation Group]] ===<br />
Prof. Matthew Guthaus' research group.<br />
<br />
=== [[Paper/Thesis Guide]] ===<br />
Some useful information on how I recommend to write/edit papers.<br />
<br />
=== [[VLSI Reading Group]] ===<br />
Starting in Winter 2008, there will be a weekly seminar (CMPE 280G) on VLSI and Design Automation. This is where the schedule and possible papers are organized.<br />
<br />
<br />
Consult the [http://meta.wikimedia.org/wiki/Help:Contents User's Guide] for information on using the wiki software.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Setup_osu180.tcl&diff=326Setup osu180.tcl2008-01-14T19:09:09Z<p>128.114.59.176: </p>
<hr />
<div><pre><br />
set LIB_NAME "osu018_stdcells"<br />
set DFF_CELL "DFFNEGX1"<br />
set LIB_DFF_D "$LIB_NAME/$DFF_CELL/D"<br />
set DFF_CKQ 0.2; # Clk to Q in technology time units <br />
set DFF_SETUP 0.0; # Setup time in technology time units <br />
<br />
# Search paths <br />
set OSUcells [format "%s%s" [getenv "OSUcells"] "/lib/tsmc018"]<br />
<br />
set search_path [concat $search_path $OSUcells]<br />
<br />
<br />
set target_library "osu018_stdcells.db"<br />
<br />
set symbol_library { }<br />
set link_library $target_library<br />
<br />
# Synthetic libraries <br />
set synlibs {"dw01.sldb" "dw02.sldb" "dw03.sldb" "dw04.sldb" "dw05.sldb" "dw06.sldb" "dw07.sldb" }<br />
set snps [get_unix_variable "SYNOPSYS"]<br />
set synthetic_library { }<br />
foreach i $synlibs {<br />
lappend synthetic_library $snps/libraries/syn/$i<br />
lappend link_library $snps/libraries/syn/$i<br />
}<br />
<br />
# don't use special clock cells for datapath logic<br />
set_dont_use [get_lib_cells "$LIB_NAME/CLK*"]<br />
</pre></div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Setup_osu180.tcl&diff=325Setup osu180.tcl2008-01-14T19:07:50Z<p>128.114.59.176: New page: <pre> set LIB_NAME "osu018_stdcells" set DFF_CELL "DFFNEGX1" set LIB_DFF_D "$LIB_NAME/$DFF_CELL/D" set DFF_CKQ 0.2; # Clk to Q in technology time units set DFF_SETUP 0.0; # ...</p>
<hr />
<div><pre><br />
set LIB_NAME "osu018_stdcells"<br />
set DFF_CELL "DFFNEGX1"<br />
set LIB_DFF_D "$LIB_NAME/$DFF_CELL/D"<br />
set DFF_CKQ 0.2; # Clk to Q in technology time units <br />
set DFF_SETUP 0.0; # Setup time in technology time units <br />
<br />
# Search paths <br />
set search_path {. /opt/osu_stdcells/lib/tsmc018/lib }<br />
<br />
set target_library { /opt/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db }<br />
set symbol_library { }<br />
set link_library $target_library<br />
<br />
# Synthetic libraries <br />
set synlibs {"dw01.sldb" "dw02.sldb" "dw03.sldb" "dw04.sldb" "dw05.sldb" "dw06.sldb" "dw07.sldb" }<br />
set snps [get_unix_variable "SYNOPSYS"]<br />
set synthetic_library { }<br />
foreach i $synlibs {<br />
lappend synthetic_library $snps/libraries/syn/$i<br />
lappend link_library $snps/libraries/syn/$i<br />
}<br />
<br />
# don't use special clock cells for datapath logic<br />
set_dont_use [get_lib_cells "$LIB_NAME/CLK*"]<br />
</pre></div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Cadence_Encounter&diff=319Cadence Encounter2008-01-14T19:03:51Z<p>128.114.59.176: New page: To use the Cadence tools, you must change this environment variable: * export OSUcells=/mada/software/techfiles/osu_soc_v2.7/cadence The OSU scripts for Cadence can be copied from h...</p>
<hr />
<div>To use the Cadence tools, you must change this environment variable:<br />
<br />
* export OSUcells=/mada/software/techfiles/osu_soc_v2.7/cadence <br />
<br />
The OSU scripts for Cadence can be copied from here:<br />
<br />
* cp -rf /mada/software/techfiles/osu_soc_v2.7/cadence/flow/tsmc018<br />
<br />
You will need to specify the correct top-level name and gate-level netlist name in encounter.conf. To place and route the design, type:<br />
<br />
* encounter -f encounter.tcl<br />
<br />
with X11 exported to your local machine. If this completes successfully, you can hit "f" to center the layout.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=318Standard-Cell Tutorials2008-01-14T19:01:33Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR><br />
# [[Cadence Encounter]]<BR><br />
<br />
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=314Standard-Cell Tutorials2008-01-14T18:12:05Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR><br />
<br />
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=313Standard-Cell Tutorials2008-01-14T18:11:52Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR><br />
<br />
For other tutorials, please see the[http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Standard-Cell_Tutorials&diff=311Standard-Cell Tutorials2008-01-14T17:56:32Z<p>128.114.59.176: </p>
<hr />
<div># [[OSU Technology Setup]]<BR><br />
# [[Synopsys Design Compiler]]<BR></div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=304VLSI Reading Group2008-01-07T22:18:30Z<p>128.114.59.176: /* Suggested Papers */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/7/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/14/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/21/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Suggested Papers==<br />
<br />
* Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003.<br />
<br />
* Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=303VLSI Reading Group2008-01-07T22:15:10Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/31/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/7/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/14/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/21/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 2/28/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/6/08<br />
| TBD<br />
| TBD <br />
|-<br />
| 3/13/08<br />
| TBD<br />
| TBD <br />
|-<br />
<br />
|}<br />
<br />
==Suggested Papers==<br />
<br />
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.<br />
<br />
* [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=302VLSI Reading Group2008-01-07T22:13:48Z<p>128.114.59.176: /* Schedule */</p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/10/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
| 1/24/08<br />
| -<br />
| NOT MEETING <br />
|-<br />
|}<br />
<br />
==Suggested Papers==<br />
<br />
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.<br />
<br />
* [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=301VLSI Reading Group2008-01-07T18:45:10Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
|}<br />
<br />
==Suggested Papers==<br />
<br />
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.<br />
<br />
* [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=300VLSI Reading Group2008-01-07T18:43:54Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 one day a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
|}<br />
<br />
==Suggested Papers==<br />
<br />
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.<br />
<br />
* [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=VLSI_Reading_Group&diff=299VLSI Reading Group2008-01-07T18:42:00Z<p>128.114.59.176: </p>
<hr />
<div>==Overview==<br />
The reading group will meet in E2-209 one day a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation.<br />
<br />
==Participants==<br />
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]<br />
<br />
==Schedule==<br />
{| border="1"<br />
|-<br />
! Date<br />
! Presenter<br />
! Paper<br />
|-<br />
| 1/17/08<br />
| Matt<br />
| M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity matching, ASPDAC, Seoul, Korea, 2008, IN PRESS. <br />
|-<br />
|}<br />
<br />
==Suggested Papers==<br />
<br />
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.<br />
<br />
* [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.<br />
<br />
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. <br />
<br />
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Exporting_GDS&diff=279Exporting GDS2007-12-11T21:59:19Z<p>128.114.59.176: </p>
<hr />
<div>To export GDS, you can go to File->Export->Stream... in the CIW.<br />
<br />
In the new window that opens up, specify a stream file.<br />
<br />
Select the technology library (NCSU_techlib_tsmc02d).<br />
<br />
Select YOUR library, top level cell and "layout" as the view.<br />
<br />
Click on "Options".<br />
<br />
Click on the "Layers" tab.<br />
<br />
Click on "Load File".<br />
<br />
Load this file of layer information:<br />
/mada/software/techfiles/NCSU_CDK_1.5.1/pipo/streamInLayermap<br />
<br />
Click on "Translate".<br />
<br />
Turn in the GDS file. TELL ME WHAT THE TOP LEVEL CELL IS.<br />
<br />
You can check that your file exported correctly by: 1) creating a new library, do a File->Import->Stream... 3) specifying the correct "top level" cell to translate. Another check is that the summary of objects is the same:<br />
<PRE><br />
Summary of Objects Translated:<br />
<br />
Instances: 5<br />
Arrays: 0<br />
Polygons: 0<br />
Paths: 8<br />
PathSegs: 0<br />
Rectangles: 44<br />
Text: 0<br />
Node: 0<br />
Line: 0<br />
Cells: 6<br />
</PRE></div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Exporting_GDS&diff=278Exporting GDS2007-12-11T21:57:17Z<p>128.114.59.176: </p>
<hr />
<div>To export GDS, you can go to File->Export->Stream... in the CIW.<br />
<br />
In the new window that opens up, specify a stream file.<br />
<br />
Select the technology library (NCSU_techlib_tsmc02d).<br />
<br />
Select YOUR library, top level cell and "layout" as the view.<br />
<br />
Click on "Options".<br />
<br />
Click on the "Layers" tab.<br />
<br />
Click on "Load File".<br />
<br />
Load this file of layer information:<br />
/mada/software/techfiles/NCSU_CDK_1.5.1/pipo/streamInLayermap<br />
<br />
Click on "Translate".<br />
<br />
Turn in the GDS file. TELL ME WHAT THE TOP LEVEL CELL IS.<br />
<br />
You can check that your file exported correctly by: 1) creating a new library, do a File->Import->Stream... 3) specifying the correct "top level" cell to translate.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Exporting_GDS&diff=277Exporting GDS2007-12-11T21:45:56Z<p>128.114.59.176: New page: To export GDS, you can go to File->Export->Stream... in the CIW. In the new window that opens up, specify a stream file. Select the technology library (NCSU_techlib_tsmc02d). Select YOU...</p>
<hr />
<div>To export GDS, you can go to File->Export->Stream... in the CIW.<br />
<br />
In the new window that opens up, specify a stream file.<br />
<br />
Select the technology library (NCSU_techlib_tsmc02d).<br />
<br />
Select YOUR library, toplevel cell and "layout" as the view.<br />
<br />
Click on "Options".<br />
<br />
Click on the "Layers" tab.<br />
<br />
Click on "Load File".<br />
<br />
Load this file of layer information:<br />
/mada/software/techfiles/NCSU_CDK_1.5.1/pipo/streamInLayermap<br />
<br />
Click on "Translate".<br />
<br />
Turn in the GDS file.</div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Full-Custom_Tutorials&diff=276Full-Custom Tutorials2007-12-11T21:43:37Z<p>128.114.59.176: </p>
<hr />
<div>[[Full-Custom FAQ]] | [[Tips for good layout]] | [http://www.eda.ncsu.edu/wiki/NCSU_CDK NCSU CDK] | [http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html MOSIS SCMOS Design Rules.] <br />
<BR><BR><br />
This page is a central location for all CAD setup at UCSC. If you find an error, FIX IT! This is a wiki so everyone can make changes. It will get out of date quickly as tools are upgraded.<BR><br />
<br />
<br />
# [[Creating a New Project]]<BR><br />
# [[INV Schematic Tutorial]]<BR><br />
# [[INV Layout Tutorial]]<BR><br />
# [[Running DRC]]<BR><br />
# [[Running LVS]]<BR><br />
# [[Debugging LVS]]<br><br />
# [[FO4_INV Example]]<br><br />
# [[UltraSim Tutorial]]<br><br />
# [[Back Annotation]]<br><br />
# [[Exporting CIF]]<br><br />
# [[Exporting GDS]]<br><br />
# [[Advanced Testbenches]]<br><br />
<br />
<br />
<br />
<br />
<br />
This was created by:<BR><br />
[[Derek Chan]]<BR><br />
[http://www.soe.ucsc.edu/~mrg Matt Guthaus]<BR></div>128.114.59.176https://vlsiwiki.soe.ucsc.edu/index.php?title=Advanced_Testbenches&diff=275Advanced Testbenches2007-12-10T21:25:11Z<p>128.114.59.176: </p>
<hr />
<div>== Introduction ==<br />
<br />
This tutorial is intended to familiarize you with one possible methodology to test your digital logic. Rather than running UltraSim and visually inspecting the results, you can run a logical (1's and 0's) simulation through the Virtuoso interface. In the previous homeworks, we made schematics using the nmos and pmos devices in the NCSU_Analog_Part library. In addition to the schematic views, these transistors have many other views including a "functional" view. The functional view allows Verilog code of your circuit to be generated from your schematic and simulated. We will simulate your schematic with NCVerilog and view the output in SimVision. Unfortunately, there is no GUI to add stimulus, so you will need to learn a small amount of verilog to design your test benches.<br />
<br />
== Writing a Test Bench ==<br />
<br />
Verilog has 4 main signal types: 1, 0, z (high impedence), and x (undefined). z will occur when nothing is driving a signal. x will occur when multiple things are driving a signal. There are some other types, but those are very infrequently used.<br />
<br />
== Ending the simulation ==<br />
<br />
When your input changes are done, run this command:<br />
<br />
#10 $finish;<br />
<br />
This will stop the simulation after one additional cycle of simulation.<br />
<br />
<br />
== Setting up Logic Simulations ==<br />
<br />
The first step is to open your schematic in Cadence Composer. Remove all of the analog elements from the previous assignments (vpulse, vpwl, vdc, etc.). You can leave the power and ground connected to the transistors in your cells, but do not have any of the "test setup" items. From the menu, select Tools->Verilog_Integration>NCVerilog. You will get a window like this:<br />
<br />
<br />
[[Image:ncverilog.jpg|400px]]<br />
<br />
<br />
<br />
If you want to change the time units from ns to ps, select Setup->Netlist. In this view, you can change the global sim time units from ns, the default, to ps. If you change the time units, I recommend that you do this for the global sim precision also. Select OK.<br />
<br />
Now click on the "running man" to initialize the design and then on the "hierarchy" button to generate the Verilog netlist from your schematic. You will have to re-do this each time you change your schematic. All of your verilog and run-files are put in the directory specified.<br />
<br />
Now, you can select Commands->Edit Test Fixture. In this you can see the test stimulus file is called "testfixture.verilog" by default. You can continue editing this (it will open the file in vi if you press OK) or you can cancel and copy the testbench you previously wrote to this file in the previous run directory (i.e. YourLibrary/nandtree_run1/testfixture.verilog). Keep backups of your testbench in case this gets over-written! It seems that when you click on the running man, it will over-write this file.<br />
<br />
After your stimulus is set up, click the "Simulate" button below the hiearchy button. This will open your verilog and testbench in SimVision. You will get two windows like this:<br />
<br />
[[Image:simvision_designbrowser.jpg|400px]]<br />
<br />
[[Image:simvision_console.jpg|400px]]<br />
<br />
If you select your module in the design browser click on the "Play" button in either window, it will run your simulation in its entirety. On the right side of the design browser, you will see the signals and their final values like this:<br />
<br />
[[Image:simvision_simran.jpg|400px]]<br />
<br />
<br />
Select the signals on the right that you wish to view and click on the "Send objects to target waveform window" button in the upper right. It is actually the 5th button from the right. This will open the waveform viewer so you can browse your results like this:<br />
<br />
[[Image:simvision_waveform.jpg|400px]]<br />
<br />
== Dumping a VCD File for UltraSim ==<br />
<br />
In class, I briefly mentioned that UltraSim can read a Verilog "dump" file. You can generate this file from your verilog simulation. Select the signals you wish to export (i.e. all top level signals). Now select File->Export. Select VCD instead of SST as the format. Change the filename to something meaningful like "mytest.vcd".<br />
<br />
<br />
== Reading a VCD File in UltraSim== <br />
<br />
Now, in UltraSim, do the normal setup, but don't add the test structures to your schematic -- this will be done witht he VCD file. Now select Setup->Simulation Files and put the path and name of the VCD file in the appropriate field. Once you do that, you can then add a VCD information file in the next field. This file is required to determine which signals are inputs and outputs, the rise/fall times, and the voltage levels. It is a format like this:<br />
<br />
.in A B C D<br />
.out Z<br />
.trise 20<br />
.tfall 20<br />
.vih 1.8<br />
.vil 0.0<br />
.voh 1.3<br />
.vol 0.5<br />
<br />
You can call it something like "mytest.info". The voltage levels are in volts. The trist and tfall times are in the same units as your Verilog simulation (ns or ps).<br />
<br />
Now, run your UltraSim simulation!<br />
<br />
<br />
== Viewing Digital Outputs ==<br />
<br />
But there's a better way to view waveforms- after some digging, here's what I ended up with:<br />
* Run the simulation while changing simulation->option->analog->OutputFormat->SST2<br />
* Use simvision to Open the resulting database (which is probably in <HOMEDIR>/Cadence/...<br />
* You get really nice waveforms, and the ability to group signals into buses which is for the adders etc.<br />
<br />
Here's a nice screenshot got from simvision, so you can see what it can do <br />
<br />
[[Image:simvision_digital.jpg|400px]]<br />
<br />
== Busses ==<br />
<br />
Busses are allowed in both Composer and Verilog. In composer, you can make a bus "pin" by just naming it, for example, "A<0:3>" for an 4-bit bus. You can add a bus pin in Composer by adding a pin like normal but using the bus name, "A<0:3>". Now, suppose you want to use only the "A<0>" bit for the input of a gate. Connect a wire from the pin as normal. Select the unique part of the wire (right by the single-bit pin, not the bus pin) and select Add->Wire Name from the menus. Input the individual bit name like "A<0". Now, you place the name with one click and then you draw a line to the wire that the name corresponds to with the second click.<br />
<br />
In your layout, you must make a pin for each bit, A<0>, A<1>, etc.<br />
<br />
In Verilog, the names use square instead of angled brackets, "A[0:3]". The most common problem with busses is assigning them in the wrong order. "A[0:3]" and "A[3:0]" are not the same. Be consistent and it won't be a problem. To the previous VCD information file, you need to append any correspondence information about bus names. For example, the inputs become<br />
<br />
.in A[0:3]<br />
<br />
And we must convert the bus naming style to one that the schematic is using with this command<br />
<br />
.alias *[*] *_*<br />
<br />
In your verilog stimulus file, you can specify busses in a number of ways. For example,<br />
<br />
eightbitbus[0:7] = 8'h0F;<br />
eightbitbus[0:7] = 8'b00001111;<br />
<br />
The first assigns 8 bits as hexidecimal. The second does it with binary.<br />
<br />
==Automatic result checking==<br />
<br />
To Automatically check result with verilog dump (VCD) file in Ultrasim,<br />
add this line in to your .info file.<br />
<br />
syntax:<br />
<PRE><br />
.chkwindow <start_time> <end_time> <steady> [period=integer] [first=integer] [signal_name1... signal_nameN ]<br />
</PRE><br />
example:<br />
<PRE><br />
.chkwindow 0 5 0 period=40 first=30 out[*]<br />
</PRE><br />
It tells ultrasim to activate periodic window of size 5 (end_time-start_time) checking for signals out[*] (signal_name). The check points start at 30 ns (first=30) and repeats every 40 ns (period=40).<br />
<br />
Then you will get a file called input.veclog in your simulationg directory<br />
cse/grads/<username>/cadence/simulation/<test_module>/UltraSim/schematic/psf/input.veclog<br />
<br />
This file is like this:<br />
<PRE><br />
****VectorCheck for out_0: All good!<br />
Number of total vector checks = 8<br />
Number of X's matched correctly = 0<br />
Number of Zero's matched correctly = 6<br />
Number of One's matched correctly = 2<br />
Number of total states matched correctly = 8<br />
Number of total errors = 0<br />
</PRE><br />
You can find how many zero or one are mached correctly.<br />
<br />
== Summary ==<br />
<br />
After this tutorial, you should be able to quickly write test benches in Verilog, run them in NCVerilog and import the results into UltraSim. This will greatly improve your ability to test your circuits.</div>128.114.59.176