View source for VLSI Reading Group

==Overview==
The reading group will meet in E2-209 one day a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation.

==Participants==
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]

==Schedule==
{| border="1"
|-
! Date
! Presenter
! Paper
|-
| 1/17/08
| Matt
| M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity matching, ASPDAC, Seoul, Korea, 2008, IN PRESS. 
|-
|}

==Suggested Papers==

* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.

* [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.

* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. 

* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.