View source for Synthesis Setup

MASC uses a unified compilation environment which requires the use of the command rake to synthesize designs.
To synthesize your design follow the steps below:

Step 1:  Create a directory, preferably named the same thing as your design top level.  

         For example: if my design is named alu, 
         I would create a directory by the name of alu.

Step 2:  Create an rtl directory inside the design directory.  

         For example: alu/rtl

Step 3:  All design rtl should reside in the rtl directory. 

         For example: alu/rtl/alu.v  alu/rtl/alu_mem.v alu/rtl/alu_fifo.v

Step 4:  In the alu directory create an xml file.  The xml file must have the same name as the directory.

         For example: alu/alu.xml

Step 5:  The xml file must contain the following tags.

         For example:
   <project name="alu">
         <requires>common</requires>
         <requires>rnet</requires>
         <requires>storage</requires>
         <requires>retry</requires>
         <asic frequency="1400" tech="90" suite="dc"/>
         <asic base="alu"/>
         <catalyst base="alu" test=""/>
         <verify base="alu"/>
         <fpga base="alu" tool="synplify"/>
         <testbench base="alu_tb" suite="vcs">
         <CC></CC>
         <verilog>tests/</verilog>
         <tab>tests/</tab>
         <source>
         </source>
         </testbench>
         <regression target="test">alu_tb</regression>
         <regression target="asic">alu</regression>
         <regression target="fpga">alu</regression>
   </project>

Step 6:  From the design directory type rake.

         For example:  (from alu/ )type "rake"
         All options for the current design should be displayed on the screen.
         
         rigo @ mada0 ~/mascrtl/projects/tapeout/alu $ rake
                      (in /mada/users/rigo/mascrtl)
                      rake all                 # Run everything!
                      rake asic:all            # Run all ASIC tasks.
                      rake asic:alu_top        # Run "alu_top" with ASIC.
                      rake catalyst:all        # Create the Catalyst directory 
                      rake catalyst:alu_top    # Create "alu_top" for Catalyst.
                      rake clean               # Remove any temporary products.
                      rake clobber             # Remove any generated file.
                      rake default             # Show a list of available tasks.
                      rake fpga:all            # Run all FPGA tasks. 
                      rake fpga:alu_top        # Run "alu_top" with "synplify" FPGA.
                      rake regression:all      # Run all regression tasks.
                      rake regression:clean    # clean all regression tasks.
                      rake regression:clobber  # clobber all regression tasks.
                      rake rverilog:all        # Create the Verilog/Ruby generated files.
                      rake test:all            # Run all test benches.
                      rake verify:all          # Run all verify tasks.
                      rake verify:alu_top      # Run "alu_top" with Formality.
                      General Options:
                      full=1         ; Let any module to be a target
                      v=1            ; Do not launch program execution
                      FPGA Options:
                      tool=num       ; synplify
                      ASIC Options:
                      tech=num       ; Technology (90, 65...)
                      frequency=num  ; Frequency in MHz (900, 140)
                      suite=string   ; ASIC suite (dc, pt, rc, soc)
                      TEST Options:
                      suite=string   ; Test suite (vsim, vcs, ncsim, gcc)
                      gui=1          ; Invoke gui for testbench (vsim, vcs)
                      console=1      ; Console Mode. (verify, dc_shell) Only with v=1.
                      do="run -all"  ; ModelSim -do line, ex do="do wave.do; run -all" (GUI Only)
                      grid=1         ; Submit testbench(s) to Sun Grid (vsim, vcs)
                      SDF=1          ; Do timing run (must compile with ASIC first)
                      SAIF=1         ; Dump a SAIF and VCD for power analysis (it could be used with SDF=1)
                      ttb=0          ; Disable automatic generation of testbench files
                      args=          ; Pass args to tb. Use Quotes to pass multiple args
                      Touch the ttb rtl file to regenerate the ttb

Step 7:  Type "rake asic:alu full=1 v=1

         Output: (in /mada/users/rigo/mascrtl)
                 ./dc_alu.sh

                 ./dct_alu.sh

                 ./dc_alu.sh

                 ./dct_alu.sh

Step 8: type ./dc_alu.sh