Difference between revisions of "280G W09"
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| 2/20/09 | | 2/20/09 | ||
| Keven | | Keven | ||
| − | | | + | | Mavroidis, I. Papaefstathiou, I. Pnevmatikatos, D. [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4297239 A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem.] |
|- | |- | ||
| 2/20/09 | | 2/20/09 | ||
| Seokjoong | | Seokjoong | ||
| − | | Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, [http://portal.acm.org/ | + | | Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, [http://portal.acm.org/ft_gateway.cfm?id=1326146&type=pdf&coll=GUIDE&dl=GUIDE&CFID=22080023&CFTOKEN=93057583 "Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping"], ICCAD 2007 version |
| − | + | Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, [http://www.cs.ucla.edu/~rupak/Papers/Efficient_SAT_based_Boolean_matching.ps "Mapping and Resynthesis for LUTbased FPGAs with an Efficient SAT-Based Boolean Matching"], International Workshop on Logic Synthesis (IWLS) 2008 version (Best Contribution Award of IEEE Programming Challenge at IWLS) | |
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| 2/27/09 | | 2/27/09 | ||
| − | | | + | | Sheldon |
| − | | | + | |Sengupta,D. and Saleh,R. [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4555800 "Application-driven Floorplan-aware Voltage Island Design"], DAC 2008 |
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| 2/27/09 | | 2/27/09 | ||
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| 5 min update | | 5 min update | ||
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| − | | 3/ | + | | 3/13/09 |
| − | | | + | | Derek |
| − | | | + | | [http://portal.acm.org/citation.cfm?id=1508128.1508139 David B. Thomas Lee Howes Wayne Luk - A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation] |
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| − | | 3/ | + | | 3/13/09 |
| Marcelo | | Marcelo | ||
| + | |Overview of HG++ (stands for either "Hierarchical G++" or my preference: "Holy Grail++". I will be presenting a summary of a C++ simulation library I have implemented. This system morphs C++ into a simulation language that looks a lot like Verilog for synchronous systems, while remaining in the C++ environment. I will go over some of the reasons why I think this has some serious advantages over existing simulation systems, and will describe its future extensions and possible uses. Critique and ideas welcome. | ||
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|- | |- | ||
| − | | | + | | 4/3/09 |
|Jeff | |Jeff | ||
|Navid Azizi, Student Member, IEEE, Farid N. Najm, Fellow, IEEE, and Andreas Moshovos, Associate Member, IEEE(IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003),[http://ieeexplore.ieee.org/ielx5/92/27561/01229876.pdf?arnumber=1229876 Low-Leakage Asymmetric-Cell SRAM], IEEE 2003 | |Navid Azizi, Student Member, IEEE, Farid N. Najm, Fellow, IEEE, and Andreas Moshovos, Associate Member, IEEE(IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003),[http://ieeexplore.ieee.org/ielx5/92/27561/01229876.pdf?arnumber=1229876 Low-Leakage Asymmetric-Cell SRAM], IEEE 2003 | ||
|- | |- | ||
| − | | 3 | + | | 4/3/09 |
| − | | | + | | Xuchu |
| − | | | + | |A.Chakraborty,P.Sithambaram,K.Duraisami,A.Macii,E.Macii,M.Poncino, DAUIN, Politecnico di Torino, ITALY, [http://portal.acm.org/citation.cfm?id=1131481.1131718 Thermal resilient Bounded-Skew Clock Tree Optimization Methodology,],DATE06 |
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Latest revision as of 21:13, 27 March 2009
- Focus primarily on ICCAD 2008 (also available on bacon in /home/www/papers/ICCAD_08).
Winter 2009
| Date | Presenter | Paper | |
|---|---|---|---|
| 1/9/09 | Meeting | ||
| 1/16/09 | Keven | Yu Hu,Shih V,Majumdar R, Lei He (University of California Los Angeles), FPGA area reduction by multi-output function based sequential resyntheis, DAC2008. | |
| 1/16/09 | Seokjoong | F. Li, D. Chen, L. He, and J. Cong (University of California Los Angeles), Architecture evaluation for power-efficient FPGAs,FPGA '03 | |
| 1/23/09 | Xuchu | Yesin Ryu, Taewhan Kim (Seoul National University),Clock Buffer Polarity Assignment Combined with Clock Tree Generation for Power/Ground Noise Minimization,ICCAD_08 | |
| 1/23/09 | Sheldon | Yong Zhan, Yan Feng, Sachin S. Sapatnekar(University of Minnesota),A Fixed Die Floorplanning Algorithm using an Analytical Approach, ASPDAC 06 | |
| 1/30/09 | Marcelo | Overview of UCI's: NISC (No Instruction Set Computer) Technology (resembles High-Level Synthesis) http://www.ics.uci.edu/~nisc
Please get these articles from: http://www.ics.uci.edu/~nisc/publications/publications.html (& look over site) Papers: #11. "Designing a Custom Architecture for DCT Using NISC Technology" (2006: pdf: 2 pages) Technical Reports, #2: TR05-11: "NISC Technology and Preliminary Results" (2005: pdf: 32 pages) | |
| 1/30/09 | Jeff | Sharifkhani, M.; Sachdev, M.(IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 2, FEBRUARY 2007),Segmented Virtual Ground Architecture for Low-Power Embedded SRAM, IEEE 2007 | |
| 2/6/09 | Derek | Topology Synthesis of Analog Circuits Based on Adaptively Generated Building Blocks Angan Das, Ranga Vemuri (Univ. of Cincinnati) | |
| 2/6/09 | Everyone | 5 min update. | |
| 2/13/09 | NO CLASS | ||
| 2/20/09 | Keven | Mavroidis, I. Papaefstathiou, I. Pnevmatikatos, D. A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem. | |
| 2/20/09 | Seokjoong | Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, "Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping", ICCAD 2007 version
Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, "Mapping and Resynthesis for LUTbased FPGAs with an Efficient SAT-Based Boolean Matching", International Workshop on Logic Synthesis (IWLS) 2008 version (Best Contribution Award of IEEE Programming Challenge at IWLS) | |
| 2/27/09 | Sheldon | Sengupta,D. and Saleh,R. "Application-driven Floorplan-aware Voltage Island Design", DAC 2008 | |
| 2/27/09 | Everyone | 5 min update | |
| 3/13/09 | Derek | David B. Thomas Lee Howes Wayne Luk - A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation | |
| 3/13/09 | Marcelo | Overview of HG++ (stands for either "Hierarchical G++" or my preference: "Holy Grail++". I will be presenting a summary of a C++ simulation library I have implemented. This system morphs C++ into a simulation language that looks a lot like Verilog for synchronous systems, while remaining in the C++ environment. I will go over some of the reasons why I think this has some serious advantages over existing simulation systems, and will describe its future extensions and possible uses. Critique and ideas welcome. | |
| 4/3/09 | Jeff | Navid Azizi, Student Member, IEEE, Farid N. Najm, Fellow, IEEE, and Andreas Moshovos, Associate Member, IEEE(IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003),Low-Leakage Asymmetric-Cell SRAM, IEEE 2003 | |
| 4/3/09 | Xuchu | A.Chakraborty,P.Sithambaram,K.Duraisami,A.Macii,E.Macii,M.Poncino, DAUIN, Politecnico di Torino, ITALY, Thermal resilient Bounded-Skew Clock Tree Optimization Methodology,,DATE06 |
