Difference between revisions of "Scheduler"
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== Scheduler Design Specifications == | == Scheduler Design Specifications == | ||
| + | FPGA Frequency Estimate (synplify_pro): 147 MHz | ||
| + | FPGA Area Estimate (synplify_pro): 14,357 LUTs | ||
| + | |||
| + | ASIC Frequency Estimate (dc_shell): 1.3 GHz | ||
| + | |||
| + | The Scheduler of SCOORE is responsible for keeping track of RAW (or true) dependencies between instructions. It is 3 stages and corresponds to stage WK1...n of the SCOORE pipeline on the Main Page. The structures that make up the long-latency Scheduler are: | ||
| + | |||
| + | 1. 64-entry instruction window | ||
| + | 2. 512 bit vector for register status | ||
| + | 3. 64-entry dependence table | ||
| + | 4. 64 bit vector for select | ||
| + | |||
| + | Details of these structures and how they are organized in the pipeline are given below. | ||
== Scheduler Interface == | == Scheduler Interface == | ||
| + | CLK and RESET are global inputs to the Scheduler | ||
| + | |||
| + | Inputs from RAT/ROB: | ||
| + | |||
| + | -clear | ||
| + | -4 instructions | ||
| + | |||
| + | Inputs from Compute Engine: | ||
| + | |||
| + | **NOTE: Compute Engine prodvides all needed information in Cunit_DoneType and MunitDoneType | ||
| + | -cunit_done | ||
| + | -cunit_pdest | ||
| + | -cunit_fault | ||
| + | |||
| + | -munit_done | ||
| + | -munit_pdest | ||
| + | -munit_fault | ||
| + | |||
| + | Inputs from Scoreboard | ||
| + | |||
| + | -busy | ||
| + | |||
| + | ---- | ||
| + | Outputs to RAT/ROB | ||
| + | |||
| + | -busy - scheduler instruction window is full | ||
| + | |||
| + | Outputs to Scoreboard | ||
| + | |||
| + | -up to 6 instructions/cycle | ||
== Unit Descriptions == | == Unit Descriptions == | ||
--[[User:Ashu Sharma|Ashu Sharma]] 18:29, 2 May 2009 (PDT) | --[[User:Ashu Sharma|Ashu Sharma]] 18:29, 2 May 2009 (PDT) | ||
Latest revision as of 19:39, 4 May 2009
Scheduler Design Specifications
FPGA Frequency Estimate (synplify_pro): 147 MHz FPGA Area Estimate (synplify_pro): 14,357 LUTs
ASIC Frequency Estimate (dc_shell): 1.3 GHz
The Scheduler of SCOORE is responsible for keeping track of RAW (or true) dependencies between instructions. It is 3 stages and corresponds to stage WK1...n of the SCOORE pipeline on the Main Page. The structures that make up the long-latency Scheduler are:
1. 64-entry instruction window
2. 512 bit vector for register status
3. 64-entry dependence table
4. 64 bit vector for select
Details of these structures and how they are organized in the pipeline are given below.
Scheduler Interface
CLK and RESET are global inputs to the Scheduler
Inputs from RAT/ROB:
-clear -4 instructions
Inputs from Compute Engine:
- NOTE: Compute Engine prodvides all needed information in Cunit_DoneType and MunitDoneType
-cunit_done -cunit_pdest -cunit_fault
-munit_done -munit_pdest -munit_fault
Inputs from Scoreboard
-busy
Outputs to RAT/ROB
-busy - scheduler instruction window is full
Outputs to Scoreboard
-up to 6 instructions/cycle
Unit Descriptions
--Ashu Sharma 18:29, 2 May 2009 (PDT)
