Difference between revisions of "Debugging LVS"
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| + | This page may be outdated. It does not use Calibre (it uses Diva), but the general methods may still apply. | ||
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LVS is annoying. It's a fact. It is a hard problem computationally and if things don't match, the debugging information it gives you is not very helpful. Here are some hints: | LVS is annoying. It's a fact. It is a hard problem computationally and if things don't match, the debugging information it gives you is not very helpful. Here are some hints: | ||
# First make sure the number of nets and devices match. If they don't, something is missing or not connected. | # First make sure the number of nets and devices match. If they don't, something is missing or not connected. | ||
# Make sure the directions of your pins in the layout and schematic match. vdd! and gnd! can be set to inputOutput in the layout and do not need pins in the schematic (they are built into the vdd and gnd components). | # Make sure the directions of your pins in the layout and schematic match. vdd! and gnd! can be set to inputOutput in the layout and do not need pins in the schematic (they are built into the vdd and gnd components). | ||
| − | # Be sure that you added ntap and ptap to the layout | + | # Be sure that you added ntap and ptap to the layout. |
# The vdd! and gnd! lines must be connected somehow. One option is to actually draw metal to connect them all. However, this must be removed when you use the "inv_test" cell later in your design. The other option is to define the pins on each disconnected net and then check the option in the Verify->Extract menu to "Join Nets With Same Name." If you do not do this, it will give you an error "2 Label/Pin vdd! is causing two nets to have the same name." The voltage source parts of the schematic are ignored during LVS. | # The vdd! and gnd! lines must be connected somehow. One option is to actually draw metal to connect them all. However, this must be removed when you use the "inv_test" cell later in your design. The other option is to define the pins on each disconnected net and then check the option in the Verify->Extract menu to "Join Nets With Same Name." If you do not do this, it will give you an error "2 Label/Pin vdd! is causing two nets to have the same name." The voltage source parts of the schematic are ignored during LVS. | ||
# Be sure that all of your vias are made with Create->Instance and NOT Create->Via. There is a problem with the setup when you define them using Create->Via which makes them seem electrically disconnected during LVS. You could get an error during LVS that Z is a floating net. | # Be sure that all of your vias are made with Create->Instance and NOT Create->Via. There is a problem with the setup when you define them using Create->Via which makes them seem electrically disconnected during LVS. You could get an error during LVS that Z is a floating net. | ||
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</pre> | </pre> | ||
These are all hints as to what did not match. In this case, check instance I9 and specifically transistor M0 in that instance is either not connected or doesn't have a counterpart in the layout. Something may not be connected to vdd! in the layout. | These are all hints as to what did not match. In this case, check instance I9 and specifically transistor M0 in that instance is either not connected or doesn't have a counterpart in the layout. Something may not be connected to vdd! in the layout. | ||
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Latest revision as of 23:09, 23 September 2009
This page may be outdated. It does not use Calibre (it uses Diva), but the general methods may still apply.
LVS is annoying. It's a fact. It is a hard problem computationally and if things don't match, the debugging information it gives you is not very helpful. Here are some hints:
- First make sure the number of nets and devices match. If they don't, something is missing or not connected.
- Make sure the directions of your pins in the layout and schematic match. vdd! and gnd! can be set to inputOutput in the layout and do not need pins in the schematic (they are built into the vdd and gnd components).
- Be sure that you added ntap and ptap to the layout.
- The vdd! and gnd! lines must be connected somehow. One option is to actually draw metal to connect them all. However, this must be removed when you use the "inv_test" cell later in your design. The other option is to define the pins on each disconnected net and then check the option in the Verify->Extract menu to "Join Nets With Same Name." If you do not do this, it will give you an error "2 Label/Pin vdd! is causing two nets to have the same name." The voltage source parts of the schematic are ignored during LVS.
- Be sure that all of your vias are made with Create->Instance and NOT Create->Via. There is a problem with the setup when you define them using Create->Via which makes them seem electrically disconnected during LVS. You could get an error during LVS that Z is a floating net.
- Another way of debugging LVS is to open the extracted cell view. This will look messy with a bunch of labels. However, you can click on the geometry of a net and it will highlight everything that the extraction thinks is connected to it.
- Yet another way of debugging is to select Connectivity->Mark Net in the layout view. Now click on a geometry shape and it will put an outline around electrically connected shapes. Connectivity->Unmark Net will undo the outline.
- If you still get an error, now examine the parts that don't match in the LVS Output (press the "Output" button next to the "Run" button in the LVS menu). You will see something like this:
Probe files from /cse/.../LVS/layout devbad.out I /I9/M0 ? Device does not cross-match. netbad.out: N /vdd! ? Net does not cross-match. It has 11 conenctions. termbad.out T -1 vdd! /vdd! ? Terminal vdd! in the schematic failed to match any terminal in the layout.
These are all hints as to what did not match. In this case, check instance I9 and specifically transistor M0 in that instance is either not connected or doesn't have a counterpart in the layout. Something may not be connected to vdd! in the layout.
