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| + | Please see the book and the [http://www.eda.ncsu.edu/wiki/FreePDK45:Contents FreePDK45] website for descriptions of the layers. |
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| − | pwell,nwell - These draw the areas for well formation. If we use a single well process, one of the layers is just thrown out.
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| − | active - The "active" layer determines the source-gate-drain locations of both NMOS and PMOS devices. The opposite of active determines where the field oxide is grown. The overlap of the active layer and the poly layer determines where the gate oxide is grown.
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| − | tactive -
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| − | nactive -
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| − | pactive -
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| − | pselect/nselect - The "P-select" layer covers the PMOS device with photoresist so that the NMOS can be ion implanted with n-type ions to form the doped source and drain. The "N-select" layer covers the NMOS device with photoresist so that the PMOS can be ion implanted with p-type ions to form the doped source and drain. Some processes (i.e. not MOSIS) do not have the select layers and instead have separate n and p active layers. The select layer is then derived from this. (This means there are only 2 instead of 3 drawn layers in these processes.)
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| − | poly -
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| − | metal1..metaln - Metal layers
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| − | cc - Contact layer between poly and metal1
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| − | via..vian - Vias between metal layers
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| − | glass - The final passivation layer. Only areas where the chip is attached to the pad ring are not covered in glass.
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Latest revision as of 20:28, 29 September 2009
Please see the book and the FreePDK45 website for descriptions of the layers.
