Difference between revisions of "Relay"
From Vlsiwiki
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I(c1,c2) <+ 0 ; | I(c1,c2) <+ 0 ; | ||
end endmodule | end endmodule | ||
| + | |||
| + | example from http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf | ||
Revision as of 22:49, 8 November 2009
module relay (c1, c2, pin, nin);
inout c1, c2;
input pin, nin;
electrical c1, c2, pin, nin;
parameter real r=1 ;
analog begin @(cross(V(pin,nin))) discontinuity(0) ;
if (V(pin,nin) >= 0)
I(c1,c2) <+ V(c1,c2)/r;
else
I(c1,c2) <+ 0 ;
end endmodule
example from http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf
