Difference between revisions of "Relay"
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| − | module relay (c1, c2, pin, nin); | + | `include "discipline.h" <br /> |
| + | `include "constants.h" <br /> | ||
| + | module relay (c1, c2, pin, nin); | ||
| + | inout c1, c2;<br /> | ||
| + | input pin, nin;<br /> | ||
| + | electrical c1, c2, pin, nin; | ||
| + | parameter real r=1 ; | ||
| + | analog begin @(cross(V(pin,nin))) discontinuity(0) ; <br /> | ||
| + | if (V(pin,nin) >= 0)<br /> | ||
| + | I(c1,c2) <+ V(c1,c2)/r; <br /> | ||
| + | else | ||
| + | I(c1,c2) <+ 0 ; | ||
| + | end endmodule | ||
| − | + | example from http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf | |
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Latest revision as of 00:19, 13 November 2009
`include "discipline.h"
`include "constants.h"
module relay (c1, c2, pin, nin); inout c1, c2;
input pin, nin;
electrical c1, c2, pin, nin; parameter real r=1 ; analog begin @(cross(V(pin,nin))) discontinuity(0) ;
if (V(pin,nin) >= 0)
I(c1,c2) <+ V(c1,c2)/r;
else I(c1,c2) <+ 0 ; end endmodule
example from http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf
