Difference between revisions of "Ultrasim and Spectre"
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For analog circuits described in Verilog - A | For analog circuits described in Verilog - A | ||
include the following command into the file that runs Ultrasim, preferably toward the end: | include the following command into the file that runs Ultrasim, preferably toward the end: | ||
| − | ahdl_include "< | + | ahdl_include "<filename>" |
To instantiate the models in the netlist, you can simply refer to it via a call to its module name. | To instantiate the models in the netlist, you can simply refer to it via a call to its module name. | ||
| Line 8: | Line 8: | ||
Verilog-A module: | Verilog-A module: | ||
| − | + | '''inverter.va | |
`include "constants.vams" | `include "constants.vams" | ||
`include "disciplines.vams" | `include "disciplines.vams" | ||
| Line 27: | Line 27: | ||
| − | + | Instantiating the module in the netlist file : '''input.ckt | |
| + | ... | ||
| + | ... | ||
... | ... | ||
I0 (input, output) inverter | I0 (input, output) inverter | ||
| Line 34: | Line 36: | ||
ahdl_include inverter.va | ahdl_include inverter.va | ||
| − | The inverter module can be used as | + | The inverter module can be used as a subckt in spectre. Parameters defined in the Verilog-A module can also be changed during instantiation such as by: |
I0 (input, output) inverter high=2.0 low=1.0 margin=1.5 | I0 (input, output) inverter high=2.0 low=1.0 margin=1.5 | ||
| + | |||
| + | |||
| + | [[Sample Buffer.ckt in Spectre]]<br /> | ||
| + | [[Sample Buffer.ckt in UltraSim]] | ||
| + | |||
| + | ==Running the Simulation== | ||
| + | Both simulators can be accessed through the Analog Design Environment GUI or via Command line. | ||
| + | |||
| + | -Ultrasim Command Line (Start in lang=spectre mode) | ||
| + | ultrasim -spectre -raw ./log_dir +log ./log_dir/ultrasim.out input.ckt | ||
| + | |||
| + | -Spectre Command Line | ||
| + | spectre -raw ./log_dir +log ./log_dir/spectre.out input.ckt | ||
Latest revision as of 07:34, 13 November 2009
For analog circuits described in Verilog - A include the following command into the file that runs Ultrasim, preferably toward the end: ahdl_include "<filename>"
To instantiate the models in the netlist, you can simply refer to it via a call to its module name.
Example:
Verilog-A module: inverter.va
`include "constants.vams"
`include "disciplines.vams"
module inverter(in, out);
input in;
output out;
electrical in, out;
parameter real high = 1.0
parameter real low = 0.0;
parameter real margin = 0.5;
analog begin
if (in < noise margin)
out = high;
else
out = low;
end
endmodule
Instantiating the module in the netlist file : input.ckt
... ... ... I0 (input, output) inverter ... ahdl_include inverter.va
The inverter module can be used as a subckt in spectre. Parameters defined in the Verilog-A module can also be changed during instantiation such as by:
I0 (input, output) inverter high=2.0 low=1.0 margin=1.5
Sample Buffer.ckt in Spectre
Sample Buffer.ckt in UltraSim
Running the Simulation
Both simulators can be accessed through the Analog Design Environment GUI or via Command line.
-Ultrasim Command Line (Start in lang=spectre mode)
ultrasim -spectre -raw ./log_dir +log ./log_dir/ultrasim.out input.ckt
-Spectre Command Line
spectre -raw ./log_dir +log ./log_dir/spectre.out input.ckt
