Difference between revisions of "VPI DEBUG"
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5life 发表于 2006-3-13 04:41 PM</p>
How to Debug PLI, DPI, and DirectC applications using gdb
NTRODUCTION:�Z*u�C�pA L!K�^*k
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You can add new functionality to a Verilog simulator such as VCS by
linking in your C code. You can also call C code from OpenVera
testbenches. Perhaps you have a C model, made of routines in the file
model.c, and invoked with the Verilog system task $model. The C code
is known as the application, and will consist of one or more routines.:T�['R!{�d)m
The connection between the application and the simulator is the PLI,
the Programming Language Interface. The application will be called
during simulation either directly, when VCS executes the system task�E�G:w�K�}-J�`(j8y X.z
for the application ($model), or asynchronously when VCS is doing an%g�D&Q�e�c*h5{3O
activity such as initialization or shutdown.
Alternately, you want to call a C routine such as log2() directly @*q8o1J�A�P�D%H
using VCS's DirectC interface, or the new DPI (Direct Procedural
Interface) that is part of SystemVerilog. Only the linking differs.
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d%B!}*d
COMPILING:
You must do several steps to debug the C application. The C code must
be compiled for debug, linked with the Verilog code, the simulator
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must be started with the debugger, and a breakpoint needs to be added�M,W3E/C�K%e5L
in the application. This guide only covers using the GNU gcc compiler�P�s�z�]�s:i:[4F/q9P3R�|
and the matching gdb debugger. Other tools will have a similar flow.�N�|$q�R#b�y
First, the C code must be compiled with -g so that its debug symbols, such%N�o;m7S#x�P�I�|�e2W
as variables and routine names, will be visible at run-time.
�E/g.|2?/A�o
> gcc -g -o model.c -I${VCS_HOME}/include�B6p!V-}�~�y%}
The -o switch tells gcc to create object code (model.o) and not an;_!`�h�A.V O�i
executable. The -I switch points to the VCS include files that define
constants and the PLI routine names.(s�U6\�v�^�|3q�W v�I&F8I B-l
�?9U�Z-w C'I�I!k"u�P
Next link the C code into your simulation:
> vcs design.v -P model.tab model.o9e�P5j�h�W'C�x
The Verilog code is in design.v, your C code is in model.o, and
model.tab tells VCS which C routines to call when $model is used in)X�F6{ e:J)e'm&d9`�~
the Verilog. This produces the executable simv.
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Alternately, you can compile the Verilog and C code together. Use the
VCS -CFLAGS option to pass flags to the C compiler: > vcs design.v -P
model.tab model.c \ -CFLAGS "-g -I${VCS_HOME}/include"
'N�{-`,^/u�g9b�]
If you are using DirectC, you don't need a table file:1C�f&W�w�z,C
O�r
> vcs +dc design.v model.o A:S3z"r�Y+c
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RUNNING THE DEBUGGER8u�w)f*b5p+n*N8\
:Z�z!m7h�_)Z
Now you are ready to roll! Start the debugger and tell it which
executable to use:�W"`�I�R�?.y�E#Q�Y�\
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O�h�S
> gdb simv
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(gdb)
Here you can set a breakpoint on a C routine:
z3{!d�r�H�V�L�w�B�}#q
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(gdb) br model_call
Breakpoint 1 at 0x8050ba6: file model.c, line 12.
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Now run the simulation, specifying the command line switches to use with simv:
(gdb) run -l simv.log�o*c6r @6V&w�M�o�E�]:K
Starting program: /disk/user/simv2q3F$I�c+c�c-^�K�`
Chronologic VCS Simulator copyright 1991-20049@�^8^$R�G�P
N�X
...6M�V�f5K$u�B�X�i4c
Breakpoint 1, model_call() at model.c:12�{3?�V$b�Z
B�t
(gdb)�n-L�@�^�q�o4l
'q�j8L�{�b)m�O)V
Now you can step through the code (step and next), print variable*}�m9x:|�E)z�_(\�_
values (print and x), look at the call stack (bt) and other debugger
tricks. If you run gdb inside Emacs (M-X gdb) you can see the source
code in one window while the debugger runs in the other.:r�k�h�Y�^�p�D
This guide only shows how to debug code linked directly with VCS, not�P�c�F�h�O/@�Y�O
shareable code. Shareable code is only loaded into memory when&q4^4W
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g�o
needed, not at the start of execution. So you can not set a�D1L$P1C
]�h
breakpoint on your code when gdb loads the executable as your code is4V-c�_!x�L�{6s�x)Q5}
not in memory yet.