Difference between revisions of "VLSI Reading Group"
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* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712. | * S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712. | ||
| − | * Other papers from ICCAD 2007. | + | * Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007]. |
Revision as of 20:27, 9 January 2008
Overview
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.
Participants
- Matthew Guthaus
- Rigo Dicochea
- Keven Woo
- Mohammed Jamil
- J. Semendari
Schedule
| Date | Presenter | Paper |
|---|---|---|
| 1/10/08 | - | NOT MEETING |
| 1/17/08 | Matt | M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS. |
| 1/24/08 | - | NOT MEETING |
| 1/31/08 | TBD | TBD |
| 2/7/08 | TBD | TBD |
| 2/14/08 | TBD | TBD |
| 2/21/08 | TBD | TBD |
| 2/28/08 | TBD | TBD |
| 3/6/08 | TBD | TBD |
| 3/13/08 | TBD | TBD |
Potential Papers
- Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003.
- Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
- A. B. Kahng, P. Sharma, and A. Zelikovsky, "Fill for Shallow Trench Isolation CMP", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668.
- S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.
- Other papers from ICCAD 2007.
