Difference between revisions of "Running LVS"

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(New page: To run LVS, you must have a schematic and a DRC clean layout. == Extract a schematic == In your layout, first perform extraction by selecting Verify->Extract. Select "Join nets with s...)
 
(→‎LVS Options)
 
(28 intermediate revisions by 4 users not shown)
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To run LVS, you must have a schematic and a DRC clean layout.  
 
To run LVS, you must have a schematic and a DRC clean layout.  
  
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== LVS Options ==
  
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== Extract a schematic ==
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Similar to DRC, LVS in SCMOS is much easier than FreePDK45, because it uses Diva instead of Calibre. Select Verify -> Extract and then Verify->LVS and then fill in your schematic and extracted views. The LVS rules should be in the technology library already.
  
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In your layout, first perform extraction by selecting Verify->Extract. Select "Join nets with same name." This command will analyze all the electrical connectivity of the different layers and create an "extracted" schematic view. This is what is compared to your schematic.
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For FreePDK45, if not done so already, Calibre->Setup->Layout Export. In the new window add the following path to the field '''User SKILL file''':
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/projects/cmpe122/techfiles/FreePDK45/ncsu_basekit/techfile/FreePDK45.tf
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Then press OK and select Calibre->Run LVS. Like the DRC setup, select the LVS rules file:
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/projects/cmpe122/techfiles/FreePDK45/ncsu_basekit/techfile/calibre/calibreLVS.rul
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In the Input section, make sure you are comparing layout and netlist. It should be hierarchical.
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Under the "Layout" tab, make sure the correct layout is selected and "Export from layout viewer" is selected. Under the "Netlist" tab make sure the correct top cell is selected and select "Export from schematic viewer".
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[[Image:1-layout.jpg|center|400px]]
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To turn on the advanced options, select Setup->LVS Options. This will add another option on the left called "LVS Options." Click it. In LVS Options, under the Supply tab, select "Ignore Layout and Source Pins during comparison". For some reason, our layout extractor is not extracting pin names at all. It will, however, make sure all the nets and transistors match correctly.
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[[Image:3-options.jpg|center|400px]]
  
 
== Running LVS ==
 
== Running LVS ==
  
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To open the LVS window, select Verify->LVS... In this window, you will need to select both your schematic and the recently generated extracted schematic. You can do this by browsing and selecting the appropriate cell views.
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Click "Run LVS" to launch the job. It may warn you about overwriting files and such. That's ok. If things go well, you should match! You will see this:
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                        #      ###################      _  _ 
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                        #        #                #      *  * 
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                  #  #        #    CORRECT    #        |   
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                    # #          #                #      \___/ 
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                    #          ###################             
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== Debugging errors ==
 
== Debugging errors ==
  
 
There is a separate wiki page, [[Debugging LVS]],  on suggestions for debugging errors. This is a very difficult problem sometimes, but it is usually a simple swap of nets or pins.
 
There is a separate wiki page, [[Debugging LVS]],  on suggestions for debugging errors. This is a very difficult problem sometimes, but it is usually a simple swap of nets or pins.

Latest revision as of 18:27, 21 March 2014

To run LVS, you must have a schematic and a DRC clean layout.

LVS Options

Similar to DRC, LVS in SCMOS is much easier than FreePDK45, because it uses Diva instead of Calibre. Select Verify -> Extract and then Verify->LVS and then fill in your schematic and extracted views. The LVS rules should be in the technology library already.

For FreePDK45, if not done so already, Calibre->Setup->Layout Export. In the new window add the following path to the field User SKILL file: 

/projects/cmpe122/techfiles/FreePDK45/ncsu_basekit/techfile/FreePDK45.tf

Then press OK and select Calibre->Run LVS. Like the DRC setup, select the LVS rules file: 

/projects/cmpe122/techfiles/FreePDK45/ncsu_basekit/techfile/calibre/calibreLVS.rul

In the Input section, make sure you are comparing layout and netlist. It should be hierarchical.

Under the "Layout" tab, make sure the correct layout is selected and "Export from layout viewer" is selected. Under the "Netlist" tab make sure the correct top cell is selected and select "Export from schematic viewer".

1-layout.jpg


To turn on the advanced options, select Setup->LVS Options. This will add another option on the left called "LVS Options." Click it. In LVS Options, under the Supply tab, select "Ignore Layout and Source Pins during comparison". For some reason, our layout extractor is not extracting pin names at all. It will, however, make sure all the nets and transistors match correctly.

3-options.jpg

Running LVS

Click "Run LVS" to launch the job. It may warn you about overwriting files and such. That's ok. If things go well, you should match! You will see this: 

                        #       ###################       _   _   
                       #        #                 #       *   *   
                  #   #         #     CORRECT     #         |     
                   # #          #                 #       \___/  
                    #           ###################


Debugging errors

There is a separate wiki page, Debugging LVS, on suggestions for debugging errors. This is a very difficult problem sometimes, but it is usually a simple swap of nets or pins.

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