Difference between revisions of "Simulation Tutorial"

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== Select Analog Environment ==
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There are many ways to simulate from Virtuoso. Which one is best depends on your PDK and your final goals.
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With the schematic file open, Ultrasim can be invoked from within icfb.  
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:Select <b>Tools &rarr; Analog Environment</b>. <br>
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At this stage, it is assumed that there is a schematic open with power sources and signal inputs defined.  Otherwise Ultrasim is going to simulate a non powered circuit which is pointless.
+
  
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[[Image:ultrasim_setup1.jpg|400px]]
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== Setting up analogLib ==
  
 +
Before you start virtuoso, make sure to add the analogLib to your libraries. Do this by editing cds.lib in your home directory (or in the project directory). You should see something like this:
  
 +
DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib
 +
DEFINE US_8ths  $CDSHOME/tools/dfII/etc/cdslib/sheets/US_8ths
 +
DEFINE basic    $CDSHOME/tools/dfII/etc/cdslib/basic
 +
DEFINE cdsDefTechLib $CDSHOME/tools/dfII/etc/cdsDefTechLib
 +
DEFINE NCSU_TechLib_FreePDK45  $PDK_DIR/ncsu_basekit/lib/NCSU_TechLib_FreePDK45
 +
DEFINE NCSU_Devices_FreePDK45  $PDK_DIR/ncsu_basekit/lib/NCSU_Devices_FreePDK45
 +
DEFINE cmpe_222_lib /mada/users/rsankara/cmpe_222_lib
  
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This is the window that pops up once Analog Environment is chosen.
 
  
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[[Image:ultrasim_setup2.jpg|400px]]
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In case your cds.lib does NOT have analogLib or one of the above libraries, then add it as follows:
 +
DEFINE  analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib
  
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== Select Simulator (<nowiki>UltraSim</nowiki>) ==
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Save the file and start virtuoso. You should see a new library in the library manager.
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Virtuoso Analog Design Environment supports various simulators such is hSpice, Spectre, and Ultrasim. Ultrasim will have to be chosen before simulations can be run. 
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:Select<b> <nowiki> Setup &rarr; Simulator/Directory/Host. </nowiki> </b>
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A follow up window will pop up giving your simulator options.
+
  
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[[Image:ultrasim_setup3.jpg|400px]]
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== Select Analog Environment ==
 +
With the schematic file open, hspice can be invoked from within Virtuoso.
 +
:Select <b>Launch &rarr; ADE L</b>. <br>
  
 +
== Select Simulator (<nowiki>hspiceD</nowiki>) ==
 +
Virtuoso Analog Design Environment supports various simulators such as hspiceD, Spectre, and Ultrasim. hspiceD was previously chosen. Now, run   
 +
:Select<b> <nowiki> Setup &rarr; Simulator/Directory/Host. </nowiki> </b>
 +
A follow up window will pop up giving your simulator options. Select '''hspiceD'''. Also specify a run directory. Press ok.
  
  
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With current settings, <tt>hspiceD is chosen by default every time Analog Environment is launched.</tt> 
 
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:Click on the Simulator button and choose <i>Ultrasim</i> .
 
  
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<b>Project Library</b> indicates where your simulation files will be stored.
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<b>Simulation Run Directory</b> indicates where your simulation files will be stored.
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The generated netlist file will be stored within <b> <nowiki> ~/cadence/simulation/YOUR SCHEMATIC/simulation/netlist/netlist </nowiki> </b>.
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The generated netlist file will be stored within in a file called "netlist".
 +
All of the other options necessary for running the simulation are stored in this directory as well in the form of separate files like netlistHeader, netlistFooter.
 +
When you run the simulation, all the options are put together by the simulator.
 +
This is useful for storing separate simulation setups for different parts of your design.
  
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<i>*It is important to note that once the simulation has been ran, it can be initiated again via the console command <br> <b> <nowiki> ~/cadence/simulation/YOUR SCHEMATIC/simulation/netlist/RUNSIMULATION </nowiki> </b>. <br> This way the netlist can be manually edited, saved, and simulated again without having to edit schematic and reinitiating ultrasim.</i>
 
  
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== Choosing Analysis Length ==
+
 
 +
== Choosing Analysis Type and Length ==
 
From the Analog Environment window  
 
From the Analog Environment window  
 
:Select <b>Analysis &rarr; Choose </b>  
 
:Select <b>Analysis &rarr; Choose </b>  
  
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This will bring up a smaller window prompting you for the duration of the simulation.
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Make sure to select tran and specify an appropriate stop time and time step (example 1ns).
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The start time is typically 0.
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[[Image:ultrasim_setup4.jpg|400px]]
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−
 
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−
 
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Make sure <b>tran</b> is selected. The other option <b>envlp</b> is for fast envelope analysis for use on RF circuits.
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Be sure to choose a stop time that is greater than the period of the input signal.
 
Be sure to choose a stop time that is greater than the period of the input signal.
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Ultrasim supports the SI prefixes so 500u would be 500 micro seconds.
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Hspice supports the SI prefixes so 500n would be 500 nano seconds.
 +
 
  
 
== Adding Model Library Files ==
 
== Adding Model Library Files ==
 
The next step is to add the spice data for the simulator.  
 
The next step is to add the spice data for the simulator.  
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:Select <b> Setup &rarr; Model Libraries </b>.  
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:Select <b> Setup &rarr; Model Library Setup </b>.  
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We will be adding the data for the Nmos and Pmos transistor using the TSMC 180nm process.
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We will be adding the data for the NMOS and PMOS transistor.
  
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[[Image:ultrasim_setup5.jpg|400px]]
 
  
 +
If you are using FreePDK as your Process Design Kit,
  
 +
Click on <i>Add File</i> and add these files:
  
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:Click on <i>browse</i> and go to: <b>/mada/software/techfiles/NCSU_CDK_1.5.1/models/hspice/public</b><br>
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$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTL.inc
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Make sure you click the .. first all the way till you see mada
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$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTL.inc
  
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:Select files
 
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:/mada/software/techfiles/NCSU_CDK_1.5.1/models/hspice/public/tsmc18dN.m
 
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:/mada/software/techfiles/NCSU_CDK_1.5.1/models/hspice/public/tsmc18dP.m
 
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:/mada/software/techfiles/NCSU_CDK_1.5.1/models/ground.sp
 
  
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Be sure to click on add after selecting each file.  Select <b> OK </b> when finished.
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Select <b> OK </b> when finished.
  
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== Selecting Outputs to be Plotted ==
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These paths will be automatically written as ".include" into a file called input.ckt
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From the Analog Environment window
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:Select <b>Outputs &rarr; To Be Plotted &rarr; Select on Schematic </b>
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Now refer back to your schematic that is open on a different window, click on various parts to add it to the output section of the Analog Design Environment Window. (for example, the output pin Z) in your schematic that you want to be plotted. Repeat this as necessary for all nets you want to see (for example, the input pin IN).
+
  
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== Running Simulation and Ouput Window ==
 
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:Select <b> Simulation  &rarr; Netlist and Run </b>
 
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This will generate the netlist file, run the simulation, and feed the results to the waveform viewer. 
 
  
 +
If you are using SCMOS(TSMC_02d) as your Process Design Kit,
 +
 +
Click on <i>Add File</i> and add these files instead:
 +
 +
/mada/software/techfiles/ncsu/models/hspice/public/tsmc18dP.m
 +
/mada/software/techfiles/ncsu/models/hspice/public/tsmc18dN.m
 +
 +
 +
Select <b> OK </b> when finished.
 +
 +
 +
 +
Perform this '''Adding Model Library Files''' step only for the process you are supposed to use. Adding multiple process files may lead to simulation problems.
 +
 +
== Running Simulation ==
 +
 +
To run a simulation, first select the type of analysis in <b>Analysis &rarr; Choose...</b> For a transient, specify the stop time (e.g. 1n).
 +
 +
It is easier to not add voltage sources to the inputs directly and instead make stimulus in a file. You can edit a stimulus file directly and include it in your simulation.
 +
Create a text file named ''stimulus.sp'' in your simulation directory and create something like this in it:
 +
 +
// Stimulus Statements Hspice format
 +
.global VDD! vdd! GND! gnd!
 +
vdd vdd! 0 vhigh
 +
.param vhigh=1200mV
 +
.param vlow=0
 +
.param tdelay=0n
 +
.param trise=5p * pick a reasonable value
 +
.param tfall=5p * pick a reasonable value
 +
.param tpulse = 10n
 +
v_A  A  0 pat (vhigh vlow tdelay trise tfall tpulse  b01010101  rb=1 r=1)
 +
C_Z Z    0 100fF * pick a reasonable value
 +
 +
The above statements define the global signals, define the '''vdd''' voltage using a parametrized statement and also some timing values.
 +
These statements may also be written in the netlist file itself if you wish to have it all in a single file.
 +
The '''.param''' statements above are used for parameterizing simulation variables. This way, if you wish to change some values for simulation, you only need to change it in the '''.param''' statement and it will take effect throughout.
 +
The '''v_A''' is a voltage source statement producing a bit stream of 01010101 as stimulus with rise,fall and pulse width times defined in the '''.param''' statements.
 +
Save the file you have now created as stimulus.sp and store it in your simulation directory.
 +
 +
To specify the stimulus, select <b>Setup &rarr; Simulation Files..</b>. and provide the path to your ''stimulus.sp''.
 +
 +
 +
For more information on Hspice commands you can look at the manual:
 +
 +
/projects/cmpe122/software/I-2013.12-1/hspice/docs_help/hspice_sa.pdf
 +
 +
== Ouput Window ==
 +
Before Running, select <b>Output &rarr; Save All...</b> to save all schematic data. (Note, this might not be best on big designs!) Or, you can select <b>Outputs &rarr; To Plot &rarr; Select on Schematic</b> and then click on all of the items on the schematic.
 +
 +
Then,
 +
:Select <b> Simulation  &rarr; Run</b>
 +
This will generate the netlist file, run the simulation, and save the results for the waveform viewer. You should re-run this every time you change your schematic.
 +
 +
You can also select <b>Simulation &rarr; Create Raw</b> to create the raw simulation file for debugging. You should be able to see your include stimulus, netlist, and a bunch of other stuff.
 +
 +
If this pops up a window that says it failed, fix the previous options. You need to debug this by looking at the output of the simulator in si.log (which is the output of running the simulator, if the simulator failed to run) or si.out (which is the actual simulator output if it ran successfully, but simulation may have failed). This will show you if it even got to the point of running the simulator.
 +
 +
 +
If it succeeded, you can select <b> Tools &rarr; Waveform  </b>. When you do this, you get three windows:
 +
 +
[[Image:waveform_graph.jpg|400px]]
 +
[[Image:waveform_browser.jpg|400px]]
 +
[[Image:waveform_results.jpg|400px]]
 +
 +
Select the "File Open" icon and then find the appropriate "raw" result file in the browser. This should open the data in the browser. Double click on the transient simulation directory and you should see signal names that correspond to your design. Double click on "A" to add it. Change the upper right option to "Append" and double click on "Z" to add it as well. If you don't change the option, it will replace the A waveform with Z. If there are problems with vdd! and gnd! you can debug that here.
 +
 +
You should get something that looks similar to this in the graph window:
  
 
[[Image:output_waveform.jpg|400px]]
 
[[Image:output_waveform.jpg|400px]]
 +
 +
Note that your signals should always rise to full vdd (1.2V) and down to gnd (0V) or else something is wrong with your logic. This is CMOS so everything is "rail to rail". It is likely an unconnected supply voltage or floating body.
  
 
== Waveform - Zooming and Trace ==
 
== Waveform - Zooming and Trace ==
Line 87: Line 153:
 
:Click on one of the waveforms in the window. This places a small label on the waveform. You can drag this marker anywhere on the waveform.
 
:Click on one of the waveforms in the window. This places a small label on the waveform. You can drag this marker anywhere on the waveform.
  
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== Power Analysis with UltraSim ==
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=== Separate Windows ===
 +
:Sometimes the window will get too cluttered. You can plot each signal in a separate window by clicking the 4th icon in the toolbar from the left to put it in "Strip Mode".
 +
 
 +
=== Reloading ===
 +
:If you make a change and resimulation, you can simply click <b> File &rarr; Reload </b>
 +
 
 +
=== Exporting Tip ===
 +
:If you intend to export the plot, it would be wise to change the background color to something other than black. In addition you can change the width of the lines by right clicking on the line and selecting properties.
 +
 
 +
== Power/Energy Analysis ==
 +
 
 +
To enable power analysis in hspice, add this statement to your stimulus file:
  
−
To enable power analysis in Ultrasim
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.measure tran toplvl_avg_power avg  power from=0ns to=100ns
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:1) go to Simulation->Options->Analog
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.measure tran toplvl_avg_energ integ power from=0ns to=100ns
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:2) In the "Advanced Checks" section, check the button near "Power analysis" and click on '''Setting'''
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.measure tran toplvl_avg_current avg I(VDD) from=0ns to=100ns
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:3) In the window that opens up
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:      3.1) Enter '''*''' for the "subckt name"
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:      3.2) Select '''max''' in the "Output Sorting" section
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:      3.3) Click on '''Add''' at the top
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:      3.4) Click '''OK''' to close the window
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:4) Click '''OK''' to close the "Simulator Options" window
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:5) Simulate as usual (Simualte->Netlist and Run)
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:6) Look for a file called "input.pa", most likely under  /cse/grads/'''USERNAME'''/cadence/simulation/comb_adder/UltraSim/schematic/psf/input.pa
+
  
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:The file will list Max,Avg and RMS power for each pin in your design, and will look something like this:
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For more information on the .measure syntax, please refer hspice user guide at:
 +
/projects/cmpe122/software/synopsys/I-2013.12-1/hspice/docs_help/hspice_sa.pdf
  
 +
You can then plot the power in the waveform viewer. It will be shown with all the other signals. In order to find the average power, you select :pwr and click on the calculator option instead of the plot option. In the calculator window, select "average" in the special functions. Then select the "Evaluate" button. (It is on the right of the "Clip" option and to the left of the Table and Append options). This will give you the average power in Watts.
  
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:
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[[Image:spectrePower.jpg|400px]]
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:*
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:*  UltraSim version 6.1.0.151  32bit 06/01/2006 18:35 (usimlx109)
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:*  Virtuoso (R) Ultrasim Full-chip Simulator
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:*  Copyright(C) 2001-2004, Cadence Design Systems, Inc.
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:*  USER: yaron  HOST: mosis4.cse.ucsc.edu  HOSTID: 7280EF31  PID: 887
+
−
:*  Memory: available: 322.0357 MB      physical: 8.3663 GB
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−
:*  CPU(1 of 4): CPU0 Dual-Core AMD Opteron(tm) Processor 2218 2613.468MHz
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:*
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:*  Netlist file: input.ckt
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:*  Starting time: Wed Nov 28 20:32:53 2007
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:*
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:
+
  
  
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:.TITLE 'This file is :../psf//input.pa'
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To enable power analysis in hspice
 +
:1) go to Simulation->Analog Options->All
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This will open a dialog box listing various Hspice analysis commands and fields for their values.
 +
Refer to Hspice documentation before using any of these options
  
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:Time: from 0n to 2000n
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== Documentation ==
  
 +
Finally, for more help...
  
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:       *** Port Current Summary *************
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:Open file: /projects/cmpe122/software/synopsys/I-2013.12-1/hspice/docs_help/hspice_sa.pdf
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:                       Max(A)          Avg(A)    RMS(A)      Peak Time(ns)
+
−
:U1_3.0      3.934e-04      -2.748e-06      2.463e-05            647.008
+
−
:U1_10.0    3.935e-04      -2.626e-06      2.443e-05            587.008
+
−
:U1_15.0    3.935e-04      -2.304e-06      2.428e-05            131.008
+
−
:U1_12.0    3.934e-04      -2.566e-06      2.419e-05            1607.01
+
−
:U1_7.0      3.933e-04      -2.667e-06      2.397e-05            1511.01
+
−
:U1_4.0      3.934e-04      -2.627e-06      2.390e-05            479.008
+
−
:U1_6.0      3.935e-04      -2.498e-06      2.385e-05            1055.01
+
−
:U1_5.0      3.935e-04      -2.562e-06      2.385e-05            851.008
+
−
:U1_11.0    3.934e-04      -2.451e-06      2.383e-05            623.008
+
−
:U1_8.0      3.934e-04      -2.705e-06      2.378e-05            1943.01
+
−
:U1_9.0      3.934e-04      -2.651e-06      2.373e-05            83.0078
+
−
:U1_13.0    3.933e-04      -2.674e-06      2.363e-05            1079.01
+
−
:U1_14.0    3.933e-04      -2.585e-06      2.325e-05            275.008
+
−
:U1_1.0      3.928e-04      -2.333e-06      2.322e-05            1379.01
+
−
:U1_0.0      3.694e-04      -2.060e-06      2.266e-05            1223.01
+
−
:U1_2.0      3.934e-04      -2.481e-06      2.256e-05            1127.01
+
−
:U1_3.B      4.652e-04      -2.657e-08      1.829e-05            1681.02
+
−
:U1_8.A      4.617e-04      -7.634e-09      1.807e-05            625.016
+
−
:U1_10.B    4.651e-04      -2.194e-08      1.773e-05            1309.02
+
−
:U1_3.vdd!          4.409e-04      2.764e-06      1.770e-05            911.02
+
−
:U1_1.A      4.618e-04      -5.062e-09      1.754e-05            289.017
+
−
:U1_15.B    4.651e-04      -3.659e-08      1.753e-05            1729.02
+
−
:U1_6.A      4.618e-04      -2.262e-08      1.740e-05            157.017
+
−
:U1_10.vdd!          4.405e-04      2.682e-06      1.730e-05            1883.02
+
−
:U1_13.B    4.651e-04      -3.209e-08      1.730e-05            1465.02
+
−
:U1_3.A      4.618e-04      -2.545e-08      1.722e-05            409.017
+
−
:U1_7.vdd!          4.403e-04      2.704e-06      1.719e-05            107.02
+
−
:U1_7.B      4.650e-04      -3.310e-08      1.717e-05            1729.02
+

Latest revision as of 22:37, 24 December 2020

There are many ways to simulate from Virtuoso. Which one is best depends on your PDK and your final goals.

Setting up analogLib

Before you start virtuoso, make sure to add the analogLib to your libraries. Do this by editing cds.lib in your home directory (or in the project directory). You should see something like this: 

DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib
DEFINE US_8ths   $CDSHOME/tools/dfII/etc/cdslib/sheets/US_8ths
DEFINE basic     $CDSHOME/tools/dfII/etc/cdslib/basic
DEFINE cdsDefTechLib $CDSHOME/tools/dfII/etc/cdsDefTechLib
DEFINE NCSU_TechLib_FreePDK45  $PDK_DIR/ncsu_basekit/lib/NCSU_TechLib_FreePDK45
DEFINE NCSU_Devices_FreePDK45  $PDK_DIR/ncsu_basekit/lib/NCSU_Devices_FreePDK45
DEFINE cmpe_222_lib /mada/users/rsankara/cmpe_222_lib


In case your cds.lib does NOT have analogLib or one of the above libraries, then add it as follows: 

DEFINE   analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib

Save the file and start virtuoso. You should see a new library in the library manager.

Select Analog Environment

With the schematic file open, hspice can be invoked from within Virtuoso.

Select Launch → ADE L.

Select Simulator (hspiceD)

Virtuoso Analog Design Environment supports various simulators such as hspiceD, Spectre, and Ultrasim. hspiceD was previously chosen. Now, run

Select Setup → Simulator/Directory/Host.

A follow up window will pop up giving your simulator options. Select hspiceD. Also specify a run directory. Press ok.


Simulation Run Directory indicates where your simulation files will be stored. The generated netlist file will be stored within in a file called "netlist". All of the other options necessary for running the simulation are stored in this directory as well in the form of separate files like netlistHeader, netlistFooter. When you run the simulation, all the options are put together by the simulator. This is useful for storing separate simulation setups for different parts of your design.


Choosing Analysis Type and Length

From the Analog Environment window

Select Analysis → Choose

Make sure to select tran and specify an appropriate stop time and time step (example 1ns). The start time is typically 0. Be sure to choose a stop time that is greater than the period of the input signal. Hspice supports the SI prefixes so 500n would be 500 nano seconds.


Adding Model Library Files

The next step is to add the spice data for the simulator.

Select Setup → Model Library Setup .

We will be adding the data for the NMOS and PMOS transistor.


If you are using FreePDK as your Process Design Kit,

Click on Add File and add these files: 

$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTL.inc
$PDK_DIR/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTL.inc


Select OK when finished.

These paths will be automatically written as ".include" into a file called input.ckt


If you are using SCMOS(TSMC_02d) as your Process Design Kit,

Click on Add File and add these files instead: 

/mada/software/techfiles/ncsu/models/hspice/public/tsmc18dP.m
/mada/software/techfiles/ncsu/models/hspice/public/tsmc18dN.m


Select OK when finished.


Perform this Adding Model Library Files step only for the process you are supposed to use. Adding multiple process files may lead to simulation problems.

Running Simulation

To run a simulation, first select the type of analysis in Analysis → Choose... For a transient, specify the stop time (e.g. 1n).

It is easier to not add voltage sources to the inputs directly and instead make stimulus in a file. You can edit a stimulus file directly and include it in your simulation. Create a text file named stimulus.sp in your simulation directory and create something like this in it: 

// Stimulus Statements Hspice format 
.global VDD! vdd! GND! gnd!
vdd vdd! 0 vhigh
.param vhigh=1200mV
.param vlow=0
.param tdelay=0n
.param trise=5p * pick a reasonable value
.param tfall=5p * pick a reasonable value
.param tpulse = 10n
v_A  A  0 pat (vhigh vlow tdelay trise tfall tpulse  b01010101  rb=1 r=1)
C_Z Z     0 100fF * pick a reasonable value

The above statements define the global signals, define the vdd voltage using a parametrized statement and also some timing values. These statements may also be written in the netlist file itself if you wish to have it all in a single file. The .param statements above are used for parameterizing simulation variables. This way, if you wish to change some values for simulation, you only need to change it in the .param statement and it will take effect throughout. The v_A is a voltage source statement producing a bit stream of 01010101 as stimulus with rise,fall and pulse width times defined in the .param statements. Save the file you have now created as stimulus.sp and store it in your simulation directory.

To specify the stimulus, select Setup → Simulation Files... and provide the path to your stimulus.sp.


For more information on Hspice commands you can look at the manual: 

/projects/cmpe122/software/I-2013.12-1/hspice/docs_help/hspice_sa.pdf

Ouput Window

Before Running, select Output → Save All... to save all schematic data. (Note, this might not be best on big designs!) Or, you can select Outputs → To Plot → Select on Schematic and then click on all of the items on the schematic.

Then,

Select Simulation → Run

This will generate the netlist file, run the simulation, and save the results for the waveform viewer. You should re-run this every time you change your schematic.

You can also select Simulation → Create Raw to create the raw simulation file for debugging. You should be able to see your include stimulus, netlist, and a bunch of other stuff.

If this pops up a window that says it failed, fix the previous options. You need to debug this by looking at the output of the simulator in si.log (which is the output of running the simulator, if the simulator failed to run) or si.out (which is the actual simulator output if it ran successfully, but simulation may have failed). This will show you if it even got to the point of running the simulator.


If it succeeded, you can select Tools → Waveform . When you do this, you get three windows:

Waveform graph.jpg Waveform browser.jpg Waveform results.jpg

Select the "File Open" icon and then find the appropriate "raw" result file in the browser. This should open the data in the browser. Double click on the transient simulation directory and you should see signal names that correspond to your design. Double click on "A" to add it. Change the upper right option to "Append" and double click on "Z" to add it as well. If you don't change the option, it will replace the A waveform with Z. If there are problems with vdd! and gnd! you can debug that here.

You should get something that looks similar to this in the graph window:

Output waveform.jpg

Note that your signals should always rise to full vdd (1.2V) and down to gnd (0V) or else something is wrong with your logic. This is CMOS so everything is "rail to rail". It is likely an unconnected supply voltage or floating body.

Waveform - Zooming and Trace

With the waveform window open, you can zoom in and find exact values.

Zoom

Select Zoom → X Zoom .
Now click and drag in the waveform window to select the x-range you want to zoom to.

Tracing

Select Marker → Place → Trace Marker

Zoom waveform.jpg

Click on one of the waveforms in the window. This places a small label on the waveform. You can drag this marker anywhere on the waveform.

Separate Windows

Sometimes the window will get too cluttered. You can plot each signal in a separate window by clicking the 4th icon in the toolbar from the left to put it in "Strip Mode".

Reloading

If you make a change and resimulation, you can simply click File → Reload

Exporting Tip

If you intend to export the plot, it would be wise to change the background color to something other than black. In addition you can change the width of the lines by right clicking on the line and selecting properties.

Power/Energy Analysis

To enable power analysis in hspice, add this statement to your stimulus file: 

.measure tran toplvl_avg_power avg   power from=0ns to=100ns
.measure tran toplvl_avg_energ integ power from=0ns to=100ns
.measure tran toplvl_avg_current avg I(VDD) from=0ns to=100ns

For more information on the .measure syntax, please refer hspice user guide at: 

/projects/cmpe122/software/synopsys/I-2013.12-1/hspice/docs_help/hspice_sa.pdf

You can then plot the power in the waveform viewer. It will be shown with all the other signals. In order to find the average power, you select :pwr and click on the calculator option instead of the plot option. In the calculator window, select "average" in the special functions. Then select the "Evaluate" button. (It is on the right of the "Clip" option and to the left of the Table and Append options). This will give you the average power in Watts.

SpectrePower.jpg


To enable power analysis in hspice

1) go to Simulation->Analog Options->All

This will open a dialog box listing various Hspice analysis commands and fields for their values. Refer to Hspice documentation before using any of these options

Documentation

Finally, for more help...

Open file: /projects/cmpe122/software/synopsys/I-2013.12-1/hspice/docs_help/hspice_sa.pdf
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