Difference between revisions of "SCOORE Coding Style"

Revision as of 00:22, 15 July 2008

Creating New Files

• When creating a new file, add the same copyright notice (GPL2). Add a module description, and the file name to the xml file

• Try to have only one module per Verilog file. The module name should match the Verilog file name

• All file names must be lowercase

• Before creating a new file check that the same functionality is not already implemented

Module Input/Output

• All the clocked modules must be a “Synchronous Moore Machine”
  • We use flops and pulse triggered latches. To make it transparent, use the “Synchronous Moore Machine” from the flops library
  • All the inputs and outputs in the module are wires. The outputs are registered using the flops library

• Flip-flops library available (storage/rtl/flop.v)
  • flop: posedge flip-flop without reset
  • flop_r: posedge flip-flop with reset. Reset_Value parameter can change the default reset value
  • cgflop: posedge flip-flop with clock gating (enable)
  • cgflop_r: posedge flip-flop with clock gating (enable) and reset

• Modules without clock signal are assumed to be combinational logic only.

• Port ordering: Declare one port per line. Use the following order:clock,reset, input (enable/busy, control, data), output (enable/busy, control data)

Clock/Reset

• Clock properties:
  • flip-flops use the posedge of the clock

• Computer resets on high reset signal. Reset signal will be high for at least 32K full clock cycles. If you need to clear a table, iterate on different clock cycles (reset high)

• Do not use any @(posedge ...) statement. If you need to use flip-flops use the flop library

flop #(.Size($bits(YourType))) 
  f1
   (.clk(clk), 
  .din(your_in),
  .q(your_out));

• Use reset signal if necessary for functionality. Not all the modules have reset signal. RAM-like structures do not have reset signal. External state machine should clear the values if necessary.

• No logic should use clock as input. Clock is only passed to structures in storage library

Blocking/Non-Blocking

• Only use blocking assignments (=)

• Combinational blocks only use blocking assignments (=). Synchronous blocks only use non-blocking assignments (<=). Since we do not have synchronous block. We only use non-blocking assignments on low level libraries like flops & memory_bank

• Use always_comb on the sensitivity list. Do not add list of parameters.

always_comb begin
  case (sel) // 
    1'b0: y = a; 
    1'b1: y = b; 
    default: y = 1'bx; 
  endcase
end

• Assign to the same variable in a single always block. Group together in the same always.

Emacs Verilog Mode

If you use emacs get verilog-mode.el and copy it to your .emacs.d directory. Then, set this options (.emacs) ("Library/Preferences/Aquamacs Emacs/Preferences.el" for Aquamacs).

 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Load verilog mode only when needed
 (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
 ;; Any files that end in .v should be in verilog mode
 (setq auto-mode-alist (cons  '("\\.v\\'" . verilog-mode) auto-mode-alist))
 ;; Any files in verilog mode should have their keywords colorized
 (add-hook 'verilog-mode-hook '(lambda () (font-lock-mode 1)))
 (add-hook 'verilog-mode-hook '(lambda () (add-hook 'local-write-file-hooks
         (lambda() (untabify (point-min) (point-max))))))
 (setq verilog-indent-level           2
     verilog-indent-level-module      2
     verilog-indent-level-declaration 2
     verilog-indent-level-behavioral  2
     verilog-indent-level-directive   1
     verilog-case-indent              2
     verilog-auto-newline             t
     verilog-auto-indent-on-newline   t
     verilog-tab-always-indent        t
     verilog-auto-endcomments         nil
     verilog-minimum-comment-distance 40
     verilog-indent-begin-after-if    t
     verilog-auto-lineup              '(all))