Difference between revisions of "FO4 INV Example"
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# This assumes that you have a cell (inv in this tutorial) that has a schematic and layout. It is also DRC clean and passes LVS. | # This assumes that you have a cell (inv in this tutorial) that has a schematic and layout. It is also DRC clean and passes LVS. | ||
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# In your schematic view, create a symbol of your design under test (inverter in this case). Design->Create Cellview->From Cellview. The defaults should be correct, but you want to convert from schematic to a symbol view. The Tool/Data Type should be Composer-Symbol. | # In your schematic view, create a symbol of your design under test (inverter in this case). Design->Create Cellview->From Cellview. The defaults should be correct, but you want to convert from schematic to a symbol view. The Tool/Data Type should be Composer-Symbol. | ||
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# Create a "inv_test" schematic and layout. In the schematic, you can place your inverter component with Add->Instance and selecting your library and inverter in the component browser. In the layout, you can place an instance of your own cell by doing a Create->Instance... and putting your library name and your cell name in the correct fields. It will then look something like this:<BR> [[Image:fo4_test.jpg|400px]] | # Create a "inv_test" schematic and layout. In the schematic, you can place your inverter component with Add->Instance and selecting your library and inverter in the component browser. In the layout, you can place an instance of your own cell by doing a Create->Instance... and putting your library name and your cell name in the correct fields. It will then look something like this:<BR> [[Image:fo4_test.jpg|400px]] | ||
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# This is simply an inverter with an fanout of 4 identical inverters. If you add the metal and vias to connect the inverters on metal2, the inv_test layout looks like this when viewing only the top level (via Display->Options). I also added input, output, and vdd/gnd ports at this level too. Make sure the FO4 schematic and layout pass DRC and LVS.<BR> [[Image:layout_setup_hierarchy.jpg|400px]] | # This is simply an inverter with an fanout of 4 identical inverters. If you add the metal and vias to connect the inverters on metal2, the inv_test layout looks like this when viewing only the top level (via Display->Options). I also added input, output, and vdd/gnd ports at this level too. Make sure the FO4 schematic and layout pass DRC and LVS.<BR> [[Image:layout_setup_hierarchy.jpg|400px]] | ||
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# Now, as you did with the inverter, create a symbol view of the FO4 test from the schematic. Instantiate it in a new schematic, called "test_setup", and set up some voltage pulse sources like this. In the schematic, the input is driven by a pulse voltage source (NCSU_Analog_Parts/Voltage_Sources/vpulse) and vdd is connected to a DC voltage source (NCSU_Analog_Parts/Voltage_Sources/vdc). I made v1=0, v2=1.8, Delay time "20p s", Rise and Fall time "20p s", pulse width "200p s", and period "500p s". The default unit of time is "s", so adding a "p" after your text turns it into picoseconds ("p s"). You will need to play with the times to get the measurements that you want.<BR> [[Image:test_setup.jpg|400px]] | # Now, as you did with the inverter, create a symbol view of the FO4 test from the schematic. Instantiate it in a new schematic, called "test_setup", and set up some voltage pulse sources like this. In the schematic, the input is driven by a pulse voltage source (NCSU_Analog_Parts/Voltage_Sources/vpulse) and vdd is connected to a DC voltage source (NCSU_Analog_Parts/Voltage_Sources/vdc). I made v1=0, v2=1.8, Delay time "20p s", Rise and Fall time "20p s", pulse width "200p s", and period "500p s". The default unit of time is "s", so adding a "p" after your text turns it into picoseconds ("p s"). You will need to play with the times to get the measurements that you want.<BR> [[Image:test_setup.jpg|400px]] | ||
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# Refer to [http://bacon.cse.ucsc.edu/wiki/index.php/UltraSim_Tutorial UltraSim Tutorial] on how to use Ultrasim to simulate the above circuit. | # Refer to [http://bacon.cse.ucsc.edu/wiki/index.php/UltraSim_Tutorial UltraSim Tutorial] on how to use Ultrasim to simulate the above circuit. | ||
Revision as of 22:38, 13 October 2008
- This assumes that you have a cell (inv in this tutorial) that has a schematic and layout. It is also DRC clean and passes LVS.
- In your schematic view, create a symbol of your design under test (inverter in this case). Design->Create Cellview->From Cellview. The defaults should be correct, but you want to convert from schematic to a symbol view. The Tool/Data Type should be Composer-Symbol.
- Create a "inv_test" schematic and layout. In the schematic, you can place your inverter component with Add->Instance and selecting your library and inverter in the component browser. In the layout, you can place an instance of your own cell by doing a Create->Instance... and putting your library name and your cell name in the correct fields. It will then look something like this:
- This is simply an inverter with an fanout of 4 identical inverters. If you add the metal and vias to connect the inverters on metal2, the inv_test layout looks like this when viewing only the top level (via Display->Options). I also added input, output, and vdd/gnd ports at this level too. Make sure the FO4 schematic and layout pass DRC and LVS.
- Now, as you did with the inverter, create a symbol view of the FO4 test from the schematic. Instantiate it in a new schematic, called "test_setup", and set up some voltage pulse sources like this. In the schematic, the input is driven by a pulse voltage source (NCSU_Analog_Parts/Voltage_Sources/vpulse) and vdd is connected to a DC voltage source (NCSU_Analog_Parts/Voltage_Sources/vdc). I made v1=0, v2=1.8, Delay time "20p s", Rise and Fall time "20p s", pulse width "200p s", and period "500p s". The default unit of time is "s", so adding a "p" after your text turns it into picoseconds ("p s"). You will need to play with the times to get the measurements that you want.
- Refer to UltraSim Tutorial on how to use Ultrasim to simulate the above circuit.
