Difference between revisions of "NALLATECH"
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=== [[Project Status]] === | === [[Project Status]] === | ||
| − | - LEON3 is booting from Onchip RAM, and sending data through the FSB. | + | - LEON3 is booting from Onchip RAM, and sending data through the FSB, using a bridge between the UART and the FSB. |
| − | - Hasim is installed | + | - Hasim is installed. |
| + | |||
| + | - Chipscope is connected to the FSB and recording the transactions between the LEON AHB bus and the FSB. | ||
| + | |||
| + | - LEON3 is booting from XEON memory and its able to execute stand-alone programs. It is 106 times slower than the same program running from internal Onchip ROM | ||
=== [[Next steps]] === | === [[Next steps]] === | ||
| − | + | ||
| − | - | + | - Use the RAM memory of the XEON for the LEON. The SRAM controller has to be attached to the FSB. |
| + | |||
The measured speed is around 64-bytes 500.000 ACP_Memcopy() operations per second. | The measured speed is around 64-bytes 500.000 ACP_Memcopy() operations per second. | ||
Since the LEON works at 100Mhz (100millions cycles per second) that not enough to support system bus. | Since the LEON works at 100Mhz (100millions cycles per second) that not enough to support system bus. | ||
Latest revision as of 00:59, 27 November 2009
http://www.nallatech.com/index.php/Intel-Xeon-FSB-Socket-Fillers/fsb-compute-module.html
Project Goals
- Implement a setup a LEON3 processor running Linux on the Nallatech board
- Set up Hasim environment
Project Status
- LEON3 is booting from Onchip RAM, and sending data through the FSB, using a bridge between the UART and the FSB.
- Hasim is installed.
- Chipscope is connected to the FSB and recording the transactions between the LEON AHB bus and the FSB.
- LEON3 is booting from XEON memory and its able to execute stand-alone programs. It is 106 times slower than the same program running from internal Onchip ROM
Next steps
- Use the RAM memory of the XEON for the LEON. The SRAM controller has to be attached to the FSB.
The measured speed is around 64-bytes 500.000 ACP_Memcopy() operations per second. Since the LEON works at 100Mhz (100millions cycles per second) that not enough to support system bus. It will be neccesary to use big caches and tranfer data in bursts.
- Setup on-board DDR-II memory
Hints to work with Nallatech System
- The only way to communicate with the system right now is through the AFU interface, using the ACP_Memcopy() function.
- Never use less than 64bytes to send and 64bytes to receive or the system will hang up.!!! - In the FPGA design you should always send back the number of bytes you declare in the ACP_Memcopy(), if not the system will hang. - The data is received and send to the FPGA in packets of 256 bits => 32 bytes. That means that each time you make a ACP_Memcopy() you will receive two packets (two rx_valid) and you must send two packets back, (two tx_valid).
