Difference between revisions of "280G S12"

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This quarter, we are going to focus on sub-threshold circuits. Here are some possible papers to cover:
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This quarter, we are going to focus on sub-threshold circuits. Participants: Jeff, Raj, Sheldon, Ben, Matt
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 +
 
 +
{| border="1"
 +
|-
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! Date
 +
! Presenter
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! Topic/Paper
 +
|-
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| 04/18/12
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| Matt
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| Sub-threshold CMOS/Device Overview
 +
|-
 +
| 04/25/12
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|Sheldon
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|[http://dl.acm.org/citation.cfm?id=1165578 Variation-driven device sizing for minimum energy sub-threshold circuits],
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[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1358745&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D1358745 Device Sizing for Minimum Energy Operation in Subthreshold Circuits]
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|-
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| 04/30/12
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| Seokjoong
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|  Dry Run
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|-
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| 05/02/12
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| NONE (Matt at GLSVLSI)
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| 
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|-
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| 05/09/12
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| Jeff
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|[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5529050&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5529050 Variability of flip-flop timing at sub-threshold voltages]
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[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5993629&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DDesign+and+Analysis+of+Metastable-Hardened+Flip-Flops+in+Sub-Threshold+Region Design and analysis of metastable-hardened flip-flops in sub-threshold region]
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|-
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| 05/16/12
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| Ben
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| [http://dl.acm.org/citation.cfm?id=1283789 Energy efficient near-threshold chip multi-processing]
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[http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS]
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|-
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| 05/23/12
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| Xuchu
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|DAC dry run
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|-
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| 05/30/12
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|  Raj
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|[http://web.eecs.umich.edu/~taustin/papers/JSSC-subliminal.pdf Exploring Variability and Performance in a Sub-200mv Processor]
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[http://delivery.acm.org/10.1145/1600000/1594240/p21-bol.pdf?ip=128.114.59.52&acc=ACTIVE%20SERVICE&CFID=81186390&CFTOKEN=41789530&__acm__=1336431606_cf92e8d9f7071a8be939365eea73ffe7 Technology Flavor Selection and Adaptive Techniques for Timing Constrained 45nm Sub-threshold Circuits]
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|-
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| 06/06/12
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|  DAC
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|
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|-
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| 06/13/12
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| Maybe?
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|
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|}
 +
 
 +
 
 +
Here are some possible papers to cover:
 +
 
 +
Theory/General:
 +
* Theoretical and practical limits of dynamic voltage scaling http://dl.acm.org/citation.cfm?id=996798
 +
* Variation-driven device sizing for minimum energy sub-threshold circuits http://dl.acm.org/citation.cfm?id=1165578
 +
* Optimal Supply and Threshold Voltage Scaling for Sub-threshold CMOS Circuits by Alice Wang, Anantha Chandrakasan, Stephen Kosonocky
 +
* A Variation Tolerant Sub-threshold Design Approach by Nikhil Jayakumar and Sunil Khatri
 +
* Technology Flavor Selection and Adaptive Techniques for Timing Constrined 45nm Sub-threshold Circuits  by David Bol and others
 +
* A 180mv Subthreshold FFT processor using a Minimum Energy Design Methodology by Alice Wang and Anantha Chandrakasan
 +
* Digital Computation in Subthreshold Region for Ultra Low Power Operation by Sumeet Kumar Gupta and others
 +
* Technologies for Ultradynamic Voltage Scaling by Anantha Chandrakasan and others
 +
* Flexible Circuits and Architectures for Ultra Low Power by Benton Calhoun and others
 +
* Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS by Benton Calhoun and others
 +
* Energy Efficient Near-Threshold Chip Multi-Processing by Bo Zhai and others
 +
* Sub-threshold Design: The challenges of minimizing circuit energy by Benton Calhoun and others
 +
* Design Considerations for Ultra Low Energy Wireless Microsensor Nodes by benton Calhoun and others
 +
* Supply and Threshold Voltage Scaling for Low Power CMOS by Ricardo Gonzalez and others
 +
* Nanometer Device Scaling in Subthreshold Logic and SRAM by Scott Hanson and others
 +
* [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4099984&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D4099984 Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures]
 +
* [http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5747457&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5747457 Radiation hardened Flip-Flop design for super and sub threshold voltage operation]
 +
* [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5993629&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DDesign+and+Analysis+of+Metastable-Hardened+Flip-Flops+in+Sub-Threshold+Region Design and analysis of metastable-hardened flip-flops in sub-threshold region]
 +
 
 +
Memories:
  
 
* Static noise margin variation for sub-threshold SRAM in 65-nm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1644879
 
* Static noise margin variation for sub-threshold SRAM in 65-nm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1644879
 
* A 256kb Sub-threshold SRAM in 65nm CMOS http://people.virginia.edu/~bhc2b/papers/Calhoun_ISSCC06.pdf
 
* A 256kb Sub-threshold SRAM in 65nm CMOS http://people.virginia.edu/~bhc2b/papers/Calhoun_ISSCC06.pdf
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* Variation-driven device sizing for minimum energy sub-threshold circuits http://dl.acm.org/citation.cfm?id=1165578
 
 
* A Sub-200mV 6T SRAM in 0.13μm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4242400
 
* A Sub-200mV 6T SRAM in 0.13μm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4242400
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* Theoretical and practical limits of dynamic voltage scaling http://dl.acm.org/citation.cfm?id=996798
+
 
−
* The sub-vth flop paper Raj showed me?
+
FPGAs:
 
* A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf
 
* A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf
 +
 +
Optimization:
 +
 +
* Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits by Benton Calhoun and others
 +
* Device Sizing for Minimum Energy Operation in Subthreshold Circuits by Benton Calhoun and others
 +
 +
Variability/Modeling:
 +
 +
* Variability of Flip-Flop Timing at Sub-Threshold Voltages" by Niklas Lotze, Maurits Ortmanns, and Yiannos Manoli
 +
* Exploring Variability and Performance in a Sub-200mv Processor by Scott Hanson and others

Latest revision as of 22:30, 9 May 2012

This quarter, we are going to focus on sub-threshold circuits. Participants: Jeff, Raj, Sheldon, Ben, Matt


Date Presenter Topic/Paper
04/18/12 Matt Sub-threshold CMOS/Device Overview
04/25/12 Sheldon Variation-driven device sizing for minimum energy sub-threshold circuits,

Device Sizing for Minimum Energy Operation in Subthreshold Circuits

04/30/12 Seokjoong Dry Run
05/02/12 NONE (Matt at GLSVLSI)
05/09/12 Jeff Variability of flip-flop timing at sub-threshold voltages

Design and analysis of metastable-hardened flip-flops in sub-threshold region

05/16/12 Ben Energy efficient near-threshold chip multi-processing

A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS

05/23/12 Xuchu DAC dry run
05/30/12 Raj Exploring Variability and Performance in a Sub-200mv Processor

Technology Flavor Selection and Adaptive Techniques for Timing Constrained 45nm Sub-threshold Circuits

06/06/12 DAC
06/13/12 Maybe?


Here are some possible papers to cover:

Theory/General:

  • Theoretical and practical limits of dynamic voltage scaling http://dl.acm.org/citation.cfm?id=996798
  • Variation-driven device sizing for minimum energy sub-threshold circuits http://dl.acm.org/citation.cfm?id=1165578
  • Optimal Supply and Threshold Voltage Scaling for Sub-threshold CMOS Circuits by Alice Wang, Anantha Chandrakasan, Stephen Kosonocky
  • A Variation Tolerant Sub-threshold Design Approach by Nikhil Jayakumar and Sunil Khatri
  • Technology Flavor Selection and Adaptive Techniques for Timing Constrined 45nm Sub-threshold Circuits by David Bol and others
  • A 180mv Subthreshold FFT processor using a Minimum Energy Design Methodology by Alice Wang and Anantha Chandrakasan
  • Digital Computation in Subthreshold Region for Ultra Low Power Operation by Sumeet Kumar Gupta and others
  • Technologies for Ultradynamic Voltage Scaling by Anantha Chandrakasan and others
  • Flexible Circuits and Architectures for Ultra Low Power by Benton Calhoun and others
  • Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS by Benton Calhoun and others
  • Energy Efficient Near-Threshold Chip Multi-Processing by Bo Zhai and others
  • Sub-threshold Design: The challenges of minimizing circuit energy by Benton Calhoun and others
  • Design Considerations for Ultra Low Energy Wireless Microsensor Nodes by benton Calhoun and others
  • Supply and Threshold Voltage Scaling for Low Power CMOS by Ricardo Gonzalez and others
  • Nanometer Device Scaling in Subthreshold Logic and SRAM by Scott Hanson and others
  • Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures
  • Radiation hardened Flip-Flop design for super and sub threshold voltage operation
  • Design and analysis of metastable-hardened flip-flops in sub-threshold region

Memories:

FPGAs:

Optimization:

  • Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits by Benton Calhoun and others
  • Device Sizing for Minimum Energy Operation in Subthreshold Circuits by Benton Calhoun and others

Variability/Modeling:

  • Variability of Flip-Flop Timing at Sub-Threshold Voltages" by Niklas Lotze, Maurits Ortmanns, and Yiannos Manoli
  • Exploring Variability and Performance in a Sub-200mv Processor by Scott Hanson and others
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