Difference between revisions of "280G F12"

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| 10/31/12
 
| 10/31/12
 
| Raj
 
| Raj
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| Standing Wave Clocking
+
|  
−
 
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=280806 Salphasic Distribution  of  Clock  Signals for  Synchronous Systems]
−
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=280806&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3Dsalphasic+clock
+
  
−
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1219105&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3D10ghz+global+clock
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1219105 Design of a IOGHz Clock Distribution Network Using Coupled Standing-Wave Oscillators]
 
|-
 
|-
 
| 11/07/12
 
| 11/07/12
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| 11/14/12
 
| 11/14/12
 
| Riadul
 
| Riadul
−
|
+
|[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4484809 Clock Distribution Scheme using Coplanar Transmission Lines]
 +
 
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5256965 A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators]
 +
 
 
|-
 
|-
 
| 11/21/12
 
| 11/21/12
 
| Ben
 
| Ben
 +
|[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1240902 Design of Resonant Global Clock Distributions]
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06332544 Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor]
 
|
 
|
 
|-
 
|-
 
| 11/28/12
 
| 11/28/12
 
| Bin
 
| Bin
−
|  
+
| [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1327750 Resonant clocking using distributed parasitic capacitance],
 +
These two are related:
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01693024 Design methodology for global resonant h-tree clock distribution networks] (Conference),
 +
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4142782 Design Methodology for Global Resonant H-Tree Clock Distribution Networks] (Journal)
 
|-
 
|-
 
| 12/05/12
 
| 12/05/12
 
| Hany
 
| Hany
 +
|[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=5937788&contentType=Conference+Publications Distributed LC resonant clock tree synthesis]
 +
 +
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6105376&contentType=Conference+Publications A methodology for local resonant clock synthesis using lc-assisted local clock buffers]
 
|
 
|
 
|}
 
|}
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! Topic/Paper
 
! Topic/Paper
 
|-
 
|-
−
| /13
+
| 1/16/13
 
| Rafael
 
| Rafael
−
|  
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| [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4476508 Resonant-Clock Latch-Based Design]
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325961 A Resonant Clock 200MHz ARM926EJ-STM Microcontroller]
 
|-
 
|-
−
| /13
+
| 1/23/13
−
| Elnaz
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| Jeff
 +
| [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1471287 A low-power SRAM with resonantly powered data, address, word, and bit lines]
 +
 
 +
|-
 +
| 1/30/13
 +
| Nihan
 +
|[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06178290 Distributed LC resonant clock grid synthesis]
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06241503 Library-aware resonant clock synthesis]
 
|
 
|
 
|-
 
|-
−
| /13
+
| 2/6/13
−
| Jeff
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|
 
|
 
|
 
|-
 
|-
−
| /13
+
| 2/13/13
−
| Nihan
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|  
 
|
 
|
 
|-
 
|-
−
| /13
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| 2/20/13
 
|  
 
|  
 
|
 
|
 
|-
 
|-
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| /13
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| 2/27/13
 
|  
 
|  
 +
|
 +
|-
 +
| 3/6/13
 +
|
 +
|
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|-
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| 3/13/13
 +
| None
 
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|}
  
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''' Resonant Papers:'''
 
''' Resonant Papers:'''
  
−
[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1374995&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D1374995 Uniform-phase uniform-amplitude resonant-load global clock distributions]
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4261012 Jitter Characteristic in Charge Recovery Resonant Clock Distribution],
  
−
[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1327750&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D1327750 Resonant clocking using distributed parasitic capacitance],
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4735565 A Resonant Global Clock Distribution for the Cell Broadband Engine Processor]
  
−
[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=4261012&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D4261012 Jitter Characteristic in Charge Recovery Resonant Clock Distribution],
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=962285 Rotary traveling-wave oscillator arrays: A new clock technology]
  
−
[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1240902&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D1240902 Design of resonant global clock distributions]
+
These might be related: [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4751849 Custom Rotary Clock Router], [http://dl.acm.org/citation.cfm?id=1529266 Custom topology rotary clock router with tree subnetworks]
  
−
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4476508 Resonant-Clock Latch-Based Design]
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4114949 1.56 GHz On-chip Resonant Clocking in 130nm CMOS]
−
 
+
−
[http://www.eecs.umich.edu/eecs/about/articles/2012/ISSCC_2012_Piledriver_final_submission.pdf Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor]
+
−
 
+
−
A. Ishii, et al., “[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325961 A Resonant Clock 200MHz ARM926EJ-STM Microcontroller],” European Solid-State Circuits Conf., pp. 356-359, 2009.
+
−
 
+
−
WOOD, J., EDWARDS, T. C., AND LIPA, S. 2001. [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=962285 Rotary traveling-wave oscillator arrays: A new clock tech- nology] . Journal of Solid-State Circuits (JSSC) 36, 11, 1654–1664.
+
−
 
+
−
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4751849 Custom Rotary Clock Router]
+
−
 
+
−
TASKIN, B., DEMAIO, J., FARELL, O., HAZELTINE, M., AND KETNER, R. 2009. [http://dl.acm.org/citation.cfm?id=1529266 Custom topology rotary clock router with tree subnetworks]. Transactions on Design Automation of Electronic Systems (TODAES) 14, 3.
+
  
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1494097 1.1 to 1.6GHz Distributed Differential Oscillator Global Clock Network]
  
 
These two would go together:
 
These two would go together:
−
GUTHAUS, M. R. 2011. [http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05937788 Distributed LC resonant clock tree synthesis]. In International Symposium on Circuits
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05937788 Distributed LC resonant clock tree synthesis],
−
and Systems (ISCAS). 1215–1218. && CONDLEY, W., HU, X., AND GUTHAUS, M. 2011. [http://dl.acm.org/citation.cfm?id=2355803 A methodology for local resonant clock synthesis using lc-assisted local clock buffers]. In International Conference on Computer-Aided Design (ICCAD). 503–506.
+
[http://dl.acm.org/citation.cfm?id=2355803 A methodology for local resonant clock synthesis using lc-assisted local clock buffers]
−
 
+
−
HU, X. AND GUTHAUS, M. 2012. [http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06178290 Distributed LC resonant clock grid synthesis]. IEEE Transactions on Circuits and Systems I (TCAS-I).
+
−
 
+
−
HU, X., CONDLEY, W., AND GUTHAUS, M. 2012. [http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06241503 Library-aware resonant clock synthesis]. In Design Automa-
+
−
tion Conference (DAC).
+
−
 
+
−
ROSENFELD, J. AND FRIEDMAN, E. 2006. [http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01693024 Design methodology for global resonant h-tree clock distribution networks]. International Symposium on Circuits and Systems (ISCAS). **there is a journal version of this too**
+
−
 
+
−
CHAN, S., RESTLE, P., SHEPARD, K., JAMES, N., AND FRANCH, R. 2004. A 4.6GHz resonant global clock distribution network. International Solid-State Circuits Conference (ISSCC), 342 – 343.
+
−
 
+
−
CHAN, S. C., SHEPARD, K. L., AND RESTLE, P. J. 2003. Design of resonant global clock distributions. International Conference on Computer Design (ICCD).
+
−
 
+
−
YU, Z. AND LIU, X. 2009. Implementing multiphase resonant clocking on a finite-impulse response filter. IEEE
+
−
Transactions on Very Large Scale Integration (VLSI) Systems 17, 11, 1593 – 1601.
+
−
 
+
−
The following are not resonant papers:
+
−
 
+
−
'''Variability:'''
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=661228&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DThe+physical+and+electrical+effects+of+metal-fill+patterning+practices+for+oxide+chemical-mechanical+polishing+processes The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=643399&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DEfficient+coupled+noise+estimation+for+on-chip+interconnects Efficient coupled noise estimation for on-chip interconnects]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=4479818&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DPractical+clock+tree+robustness+signoff+metrics Practical clock tree robustness signoff metrics]
+
−
 
+
−
[http://dl.acm.org/citation.cfm?id=640000.640037&coll=DL&dl=ACM&CFID=178850743&CFTOKEN=33089288 Process variation aware clock tree routing]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=arnumber=806506contentType=Conference+PublicationssearchField%3DSearch_All%26queryText%3DA+quadratic+programming+approach+to+clock+skew+scheduling+for+reduced+sensitivity+to+process+parameter+variations A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations]
+
−
 
+
−
'''SSTA:'''
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1257875&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DStatistical+timing+analysis+considering+spatial+correlations+using+a+single+PERT-like+traversal Statistical timing analysis considering spatial correlations using a single PERT-like traversal]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1225815&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DStatistical+timing+analysis+using+bounds+and+selective+enumeration Statistical timing analysis using bounds and selective enumeration]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1677699&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DFirst-order+incremental+block-based+statistical+timing+analysis First-order incremental block-based statistical timing analysis]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=4359932&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DStatistical+timing+analysis%3A+From+basic+principles+to+state+of+the+art Statistical timing analysis: From basic principles to state of the art]
+
−
 
+
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[http://www.sciencedirect.com/science/article/pii/S0167926008000564 Statistical static timing analysis: A survey]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1257916&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DStatistical+clock+skew+analysis+considering+intra-die+process+variations Statistical clock skew analysis considering intra-die process variations]
+
−
 
+
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[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1410616&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DStatistical+analysis+of+clock+skew+variation+in+H-tree+structure Statistical analysis of clock skew variation in H-tree structure]
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−
 
+
−
'''Implementation:'''
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−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=992977&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DThe+clock+distribution+of+the+POWER4+microprocessor The clock distribution of the POWER4 microprocessor]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1696203&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DA+5GHz+duty-cycle+correcting+clock+distribution+network+for+the+POWER6+microprocessor A 5GHz duty-cycle correcting clock distribution network for the POWER6 microprocessor]
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−
 
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[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=912694&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DMulti-GHz+clocking+scheme+for+Intel+Pentium+4+microprocessor Multi-GHz clocking scheme for Intel Pentium 4 microprocessor]
+
−
 
+
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[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6105340&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DMyth+busters%3A+Microprocessor+clocking+is+from+mars%2C+asic%E2%80%99s+clocking+is+from+venus%3F Myth busters: Microprocessor clocking is from mars, asic’s clocking is from venus?]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=726547&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DClocking+design+and+analysis+for+a+600-MHz+Alpha+microprocessor Clocking design and analysis for a 600-MHz Alpha microprocessor]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=475708&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DA+300-MHz+64-b+quad-issue+CMOS+RISC+microprocessor A 300-MHz 64-b quad-issue CMOS RISC microprocessor]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=200434&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DA+200-MHz+64-b+dual-issue+CMOS+microprocessor A 200-MHz 64-b dual-issue CMOS microprocessor]
+
−
 
+
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=912693&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DThe+design+and+analysis+of+the+clock+distribution+network+for+a+1.2GHz+alpha+microprocessor The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor]
+
−
 
+
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'''Other:'''
+
  
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=929649&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DClock+distribution+networks+in+synchronous+digital+integrated+circuits Clock distribution networks in synchronous digital integrated circuits]
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06178290 Distributed LC resonant clock grid synthesis]
  
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=55696&contentType=Journals+%26+MagazinessearchWithin%3Dp_Authors%3A.QT.Fishburn%2C+J.P..QT.%26refinements%3D4294947175%26sortType%3Dasc_p_Publication_Year%26searchField%3DSearch_All Clock skew optimization]
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06241503 Library-aware resonant clock synthesis]
  
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=503938&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DPost-processing+of+clock+trees+via+wiresizing+and+buffering+for+robust+design Post-processing of clock trees via wiresizing and buffering for robust design]
 
  
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1560135&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DPractical+techniques+to+reduce+skew+and+its+variations+in+buffered+clock+networks Practical techniques to reduce skew and its variations in buffered clock networks]
+
These might be related:
 +
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1332734 A 4.6GHz resonant global clock distribution network],
 +
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1240902 Design of resonant global clock distributions],
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1374995 Uniform-phase uniform-amplitude resonant-load global clock distributions],
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4735565 A Resonant Global Clock Distribution for the Cell Broadband Engine Processor]
  
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1167599&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DGeneral+framework+for+removal+of+clock+network+pessimism General framework for removal of clock network pessimism]
 
  
−
[http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.8567 Performance optimization of vlsi interconnect layout]
+
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04895681 Implementing multiphase resonant clocking on a finite-impulse response filter]

Latest revision as of 21:25, 24 January 2013

This quarter, we will put a focus on resonant and non-traditional clocking. We will have two presenters each day -- about 30-40 min each. Please select papers on either distributed/monolithic LC, rotary clocking, or standing wave clocking or similar non-traditional clocking papers.


Date Presenter Topic/Paper
10/03/12 Raj,Blake,Seokjoong VLSI-SOC Dry Run ** Will need to start at 10:30am sharp
10/10/12 NONE (VLSI-SoC)
10/17/12 NONE (Matt at NSF)
10/24/12 Matt How to review papers, Read the clock survey I wrote
10/31/12 Raj

Salphasic Distribution of Clock Signals for Synchronous Systems

Design of a IOGHz Clock Distribution Network Using Coupled Standing-Wave Oscillators

11/07/12 NONE (Matt at ICCAD)
11/14/12 Riadul Clock Distribution Scheme using Coplanar Transmission Lines 
A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators
11/21/12 Ben Design of Resonant Global Clock Distributions

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

11/28/12 Bin Resonant clocking using distributed parasitic capacitance,

These two are related: Design methodology for global resonant h-tree clock distribution networks (Conference), Design Methodology for Global Resonant H-Tree Clock Distribution Networks (Journal)

12/05/12 Hany Distributed LC resonant clock tree synthesis

A methodology for local resonant clock synthesis using lc-assisted local clock buffers


Date Presenter Topic/Paper
1/16/13 Rafael Resonant-Clock Latch-Based Design

A Resonant Clock 200MHz ARM926EJ-STM Microcontroller

1/23/13 Jeff A low-power SRAM with resonantly powered data, address, word, and bit lines
1/30/13 Nihan Distributed LC resonant clock grid synthesis

Library-aware resonant clock synthesis

2/6/13
2/13/13
2/20/13
2/27/13
3/6/13
3/13/13 None


Resonant Papers:

Jitter Characteristic in Charge Recovery Resonant Clock Distribution,

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor

Rotary traveling-wave oscillator arrays: A new clock technology

These might be related: Custom Rotary Clock Router, Custom topology rotary clock router with tree subnetworks

1.56 GHz On-chip Resonant Clocking in 130nm CMOS

1.1 to 1.6GHz Distributed Differential Oscillator Global Clock Network

These two would go together: Distributed LC resonant clock tree synthesis, A methodology for local resonant clock synthesis using lc-assisted local clock buffers

Distributed LC resonant clock grid synthesis

Library-aware resonant clock synthesis


These might be related: A 4.6GHz resonant global clock distribution network, Design of resonant global clock distributions, Uniform-phase uniform-amplitude resonant-load global clock distributions, A Resonant Global Clock Distribution for the Cell Broadband Engine Processor


Implementing multiphase resonant clocking on a finite-impulse response filter

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