Difference between revisions of "280G F12"

From Vlsiwiki
Jump to: navigation, search
 
(13 intermediate revisions by 5 users not shown)
Line 45: Line 45:
 
| 11/21/12
 
| 11/21/12
 
| Ben
 
| Ben
−
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1240902 Design of Resonant Global Clock Distributions]
+
|[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1240902 Design of Resonant Global Clock Distributions]
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06332544 Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor]
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06332544 Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor]
 
|
 
|
Line 51: Line 51:
 
| 11/28/12
 
| 11/28/12
 
| Bin
 
| Bin
−
|  
+
| [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1327750 Resonant clocking using distributed parasitic capacitance],
 +
These two are related:
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01693024 Design methodology for global resonant h-tree clock distribution networks] (Conference),
 +
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4142782 Design Methodology for Global Resonant H-Tree Clock Distribution Networks] (Journal)
 
|-
 
|-
 
| 12/05/12
 
| 12/05/12
 
| Hany
 
| Hany
 +
|[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=5937788&contentType=Conference+Publications Distributed LC resonant clock tree synthesis]
 +
 +
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6105376&contentType=Conference+Publications A methodology for local resonant clock synthesis using lc-assisted local clock buffers]
 
|
 
|
 
|}
 
|}
Line 65: Line 71:
 
! Topic/Paper
 
! Topic/Paper
 
|-
 
|-
−
| /13
+
| 1/16/13
 
| Rafael
 
| Rafael
−
|  
+
| [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4476508 Resonant-Clock Latch-Based Design]
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325961 A Resonant Clock 200MHz ARM926EJ-STM Microcontroller]
 
|-
 
|-
−
| /13
+
| 1/23/13
−
| Elnaz
+
| Jeff
 +
| [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1471287 A low-power SRAM with resonantly powered data, address, word, and bit lines]
 +
 
 +
|-
 +
| 1/30/13
 +
| Nihan
 +
|[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06178290 Distributed LC resonant clock grid synthesis]
 +
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06241503 Library-aware resonant clock synthesis]
 
|
 
|
 
|-
 
|-
−
| /13
+
| 2/6/13
−
| Jeff
+
|
 
|
 
|
 
|-
 
|-
−
| /13
+
| 2/13/13
−
| Nihan
+
|  
 
|
 
|
 
|-
 
|-
−
| /13
+
| 2/20/13
 
|  
 
|  
 
|
 
|
 
|-
 
|-
−
| /13
+
| 2/27/13
 
|  
 
|  
 +
|
 +
|-
 +
| 3/6/13
 +
|
 +
|
 +
|-
 +
| 3/13/13
 +
| None
 
|}
 
|}
  
  
 
''' Resonant Papers:'''
 
''' Resonant Papers:'''
−
 
−
 
−
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1327750 Resonant clocking using distributed parasitic capacitance],
 
  
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4261012 Jitter Characteristic in Charge Recovery Resonant Clock Distribution],
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4261012 Jitter Characteristic in Charge Recovery Resonant Clock Distribution],
−
 
−
[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4476508 Resonant-Clock Latch-Based Design]
 
−
 
−
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6332544 Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor]
 
−
 
−
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325961 A Resonant Clock 200MHz ARM926EJ-STM Microcontroller]
 
  
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4735565 A Resonant Global Clock Distribution for the Cell Broadband Engine Processor]
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4735565 A Resonant Global Clock Distribution for the Cell Broadband Engine Processor]
Line 121: Line 134:
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06241503 Library-aware resonant clock synthesis]
 
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=06241503 Library-aware resonant clock synthesis]
  
−
These two are related:
 
−
[http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01693024 Design methodology for global resonant h-tree clock distribution networks] (Conference),
 
−
[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4142782 Design Methodology for Global Resonant H-Tree Clock Distribution Networks] (Journal)
 
  
 
These might be related:
 
These might be related:

Latest revision as of 21:25, 24 January 2013

This quarter, we will put a focus on resonant and non-traditional clocking. We will have two presenters each day -- about 30-40 min each. Please select papers on either distributed/monolithic LC, rotary clocking, or standing wave clocking or similar non-traditional clocking papers.


Date Presenter Topic/Paper
10/03/12 Raj,Blake,Seokjoong VLSI-SOC Dry Run ** Will need to start at 10:30am sharp
10/10/12 NONE (VLSI-SoC)
10/17/12 NONE (Matt at NSF)
10/24/12 Matt How to review papers, Read the clock survey I wrote
10/31/12 Raj

Salphasic Distribution of Clock Signals for Synchronous Systems

Design of a IOGHz Clock Distribution Network Using Coupled Standing-Wave Oscillators

11/07/12 NONE (Matt at ICCAD)
11/14/12 Riadul Clock Distribution Scheme using Coplanar Transmission Lines 
A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators
11/21/12 Ben Design of Resonant Global Clock Distributions

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

11/28/12 Bin Resonant clocking using distributed parasitic capacitance,

These two are related: Design methodology for global resonant h-tree clock distribution networks (Conference), Design Methodology for Global Resonant H-Tree Clock Distribution Networks (Journal)

12/05/12 Hany Distributed LC resonant clock tree synthesis

A methodology for local resonant clock synthesis using lc-assisted local clock buffers


Date Presenter Topic/Paper
1/16/13 Rafael Resonant-Clock Latch-Based Design

A Resonant Clock 200MHz ARM926EJ-STM Microcontroller

1/23/13 Jeff A low-power SRAM with resonantly powered data, address, word, and bit lines
1/30/13 Nihan Distributed LC resonant clock grid synthesis

Library-aware resonant clock synthesis

2/6/13
2/13/13
2/20/13
2/27/13
3/6/13
3/13/13 None


Resonant Papers:

Jitter Characteristic in Charge Recovery Resonant Clock Distribution,

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor

Rotary traveling-wave oscillator arrays: A new clock technology

These might be related: Custom Rotary Clock Router, Custom topology rotary clock router with tree subnetworks

1.56 GHz On-chip Resonant Clocking in 130nm CMOS

1.1 to 1.6GHz Distributed Differential Oscillator Global Clock Network

These two would go together: Distributed LC resonant clock tree synthesis, A methodology for local resonant clock synthesis using lc-assisted local clock buffers

Distributed LC resonant clock grid synthesis

Library-aware resonant clock synthesis


These might be related: A 4.6GHz resonant global clock distribution network, Design of resonant global clock distributions, Uniform-phase uniform-amplitude resonant-load global clock distributions, A Resonant Global Clock Distribution for the Cell Broadband Engine Processor


Implementing multiphase resonant clocking on a finite-impulse response filter

Retrieved from "https://vlsiwiki.soe.ucsc.edu/index.php?title=280G_F12&oldid=4513"