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| − | ==Verilog-A == | + | ==[[Verilog-A]] == |
| − | Verilog-A | + | The following sections provide an overview to Verilog-A, |
| + | ===What is Verilog-A=== | ||
| + | |||
| + | Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. | ||
| + | Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project. | ||
| + | Unfortunately, there was considerable delay between the first Verilog-A LRM and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera. Hence, the original goal of a single language standard is still to be achieved | ||
| + | Brief List of Functions Available in Verilog-A | ||
| + | |||
| + | Taken from http://en.wikipedia.org/wiki/Verilog-A | ||
| + | |||
| + | ===Coding Examples=== | ||
| + | Verilog-A code is structured similarly to Verilog. The structure is similar with Verilog. | ||
| + | |||
| + | The following two lines must be included at the beginning of the Verilog-A file as it defines the electrical type for for the Spectre/Ultrasim | ||
| + | `include "constants.vams" | ||
| + | `include "disciplines.vams" | ||
| + | |||
| + | Modules can be defined using: | ||
| + | |||
| + | module <module name> ( <connection 1>, <connection 2>, ... <connection n> ) | ||
| + | input <connection 1>, <connection 2>; | ||
| + | output <connection 3>, ... , <connection n>; | ||
| + | electrical <connection 1>, ... , <connection n>; | ||
| + | parameter <variable type> <parameter 1>; | ||
| + | ... | ||
| + | analog begin | ||
| + | <insert code here> | ||
| + | end | ||
| + | endmodule | ||
| + | ====Cadence AHDL Library==== | ||
| + | Cadence provides a library of sample AHDL modules and the list is very extensive. This can be found in | ||
| + | $CDS_ROOT/dfII/samples/artist/ahdlLib. | ||
| + | This can be added to the list of libraries loaded at startup for Virtuoso design suite. | ||
| + | |||
| + | ====Sample Modules==== | ||
| + | [[Relay.va]] <br /> | ||
| + | [[Resistor.va]] | ||
| + | |||
| + | ===Simulators=== | ||
| + | -[[Ultrasim and Spectre]] | ||
| + | |||
| + | ===Resources=== | ||
| + | *http://www.eigroup.org/cmc/veriloga/default.htm | ||
| + | *http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf | ||
| + | |||
| + | ==[[Verilog-AMS]]== | ||
| + | Verilog-AMS | ||
Latest revision as of 07:30, 13 November 2009
Contents
Verilog-A
The following sections provide an overview to Verilog-A,
What is Verilog-A
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project. Unfortunately, there was considerable delay between the first Verilog-A LRM and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera. Hence, the original goal of a single language standard is still to be achieved Brief List of Functions Available in Verilog-A
Taken from http://en.wikipedia.org/wiki/Verilog-A
Coding Examples
Verilog-A code is structured similarly to Verilog. The structure is similar with Verilog.
The following two lines must be included at the beginning of the Verilog-A file as it defines the electrical type for for the Spectre/Ultrasim
`include "constants.vams" `include "disciplines.vams"
Modules can be defined using:
module <module name> ( <connection 1>, <connection 2>, ... <connection n> ) input <connection 1>, <connection 2>; output <connection 3>, ... , <connection n>; electrical <connection 1>, ... , <connection n>; parameter <variable type> <parameter 1>; ... analog begin <insert code here> end endmodule
Cadence AHDL Library
Cadence provides a library of sample AHDL modules and the list is very extensive. This can be found in
$CDS_ROOT/dfII/samples/artist/ahdlLib.
This can be added to the list of libraries loaded at startup for Virtuoso design suite.
Sample Modules
Simulators
Resources
- http://www.eigroup.org/cmc/veriloga/default.htm
- http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf
Verilog-AMS
Verilog-AMS
