Difference between revisions of "Verilog-A"
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(New page: =Sample Cadence Verilog-A Library = Add the following to your libraries to gain access to the Cadence sample library /mada/software/cadence/ICOA5251/tools.lnx86/dfII/samples/artist/ahdlLib) |
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=Sample Cadence Verilog-A Library = | =Sample Cadence Verilog-A Library = | ||
Add the following to your libraries to gain access to the Cadence sample library | Add the following to your libraries to gain access to the Cadence sample library | ||
| − | /mada/software/cadence/ICOA5251/tools.lnx86/dfII/samples/artist/ahdlLib | + | |
| + | /mada/software/cadence/ICOA5251/tools.lnx86/dfII/samples/artist/ahdlLib | ||
| + | |||
| + | =Spectre Netlist = | ||
| + | Add the following command to allow spectre or ultrasim to compile Verilog-A files. | ||
| + | |||
| + | ahdl_include "<filename>" | ||
| + | |||
| + | == Simulating Verilog-A in Ultrasim == | ||
| + | |||
| + | For analog circuits described in Verilog - A | ||
| + | |||
| + | include the following command into the file that runs Ultrasim: | ||
| + | |||
| + | ahdl_include "<file>" | ||
| + | |||
| + | The verilog-a module can be instantiated in the netlist using the name of the module. | ||
| + | |||
| + | <Instance name> (port1, port2, port3) <module name> | ||
Latest revision as of 21:50, 3 May 2008
Sample Cadence Verilog-A Library
Add the following to your libraries to gain access to the Cadence sample library
/mada/software/cadence/ICOA5251/tools.lnx86/dfII/samples/artist/ahdlLib
Spectre Netlist
Add the following command to allow spectre or ultrasim to compile Verilog-A files.
ahdl_include "<filename>"
Simulating Verilog-A in Ultrasim
For analog circuits described in Verilog - A
include the following command into the file that runs Ultrasim:
ahdl_include "<file>"
The verilog-a module can be instantiated in the netlist using the name of the module.
<Instance name> (port1, port2, port3) <module name>
