Difference between revisions of "Back Annotation"

From Vlsiwiki
Jump to: navigation, search
(→‎Easier Method)
(→‎FreePDK45 Method)
 
(34 intermediate revisions by 5 users not shown)
Line 1: Line 1:
−
The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. Spectre (or hSpice) will by default use the gate area (L and W) to estimate the gate capacitance. If there are perimeters (ps, pd) and areas (as, ad) of the source and drain like this:
+
The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. Spectre (or hSpice) will by default use the gate area (L and W) to estimate the gate capacitance, but additional poly is not considered. If you specified perimeters (ps, pd) and areas (as, ad) in the pcell form, it will include those estimates in simulation. However, it does not include any extra routing, contacts, diffusion, etc. In order to include these, you need to perform parasitic extraction and back-annotation. The extraction is similar to the device extraction you used to extract a netlist for LVS, but now it extracts parasitic resistances and capacitances too.
  
−
m0 (Z A vdd vdd) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 \
+
Your design must pass DRC and LVS to do this.
−
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
+
  
−
it will  include those capacitances. However, it does not include any extra routing, contacts, diffusion, etc. In order to include these, you need to perform extraction and back-annotation. The extraction is similar to the device extraction you used to extract a netlist for LVS, but now it extracts parasitic devices too.
+
== SCMOS Method ==
−
 
+
−
== Easier Method ==
+
  
 
In order to include the extra interconnect parasitics, we must have done DRC, Extract, and LVS. There can be absolutely no errors or warnings in LVS. For example, even this doesn't allow back-annotation:
 
In order to include the extra interconnect parasitics, we must have done DRC, Extract, and LVS. There can be absolutely no errors or warnings in LVS. For example, even this doesn't allow back-annotation:
Line 52: Line 49:
  
  
−
Now, you are ready to back-annotate. In the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.  
+
Now, you are ready to back-annotate. However, in order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.  
  
−
Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Spectre simulation as normal. (In fact, you can just load the saved setup from the spectre.run1 directory.) Confirm that it works for the schematic. Then, go to Spectre->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:
+
After re-running LVS, in the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.
 +
 
 +
Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Hspice simulation as normal. (In fact, you can just load the saved setup from the Hspice run directory.) Confirm that it works for the schematic. Then, go to Hspice->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:
  
 
[[Image:simulatebackannotated.jpg|400px]]
 
[[Image:simulatebackannotated.jpg|400px]]
Line 60: Line 59:
 
Now it should have parasitics too!
 
Now it should have parasitics too!
  
−
To confirm this, look in your run directory (e.g. spectre.run1) and view the "netlist" file in the unix shell. This should have capacitances in it. If not, there is something wrong.
+
To confirm this, look in your run directory after you run a back-annotated simulation and view the "netlist" file in the unix shell and you should see a bunch of transistors and capacitors. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter:
  
−
== Old Method ==
+
// Library name: mylib
−
In order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.  
+
// Cell name: invx1
 +
// View name: analog_extracted
 +
\+1 (Z A vdd! vdd!) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
 +
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat
 +
\+5 (A 0) capacitor c=2.27853e-17 m=1
 +
\+4 (Z 0) capacitor c=2.87838e-17 m=1
 +
\+3 (vdd! 0) capacitor c=1.29997e-16 m=1
 +
\+2 (vdd! Z) capacitor c=2.87838e-17 m=1
 +
\+0 (Z A 0 0) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
 +
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat
  
−
In order to simulate with the new extracted view, open it like you would a layout. It will open up but look ugly. Load the simulation environment just like you would in the [[Simulation Tutorial]].
+
If you do not see the capacitors, then something is wrong.
  
−
Run the netlist/simulate once and then view the netlist. Open the "netlist" file. You should see a bunch of transistors and capacitors but with some randomized names. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter:
+
== FreePDK45 Method ==
  
−
  // Library name: mylib
+
This is very similar to LVS. Go to Calibre->Run PEX. You will need to specify a layer map like LVS again. Also, select the rule file as this:
−
  // Cell name: invx1
+
 
−
  // View name: extracted
+
  /projects/cmpe122/techfiles/FreePDK45/ncsu_basekit/techfile/calibre/calibrexRC.rul
−
  \+1 (Z A _net0 _net0) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 \
+
 
−
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
+
Under the Input section, in the Layout tab, make sure that GDSII and "Export from layout viewer" are selected. Under the Netlist tab, make sure that SPICE and "Export from schematic viewer" are selected.
−
  \+5 (A _net1) capacitor c=2.27853e-17 m=1
+
 
−
  \+4 (Z _net1) capacitor c=2.87838e-17 m=1
+
Under the Output section, most options should be left as default. Under Netlist, we want Hspice format and names from the SCHEMATIC. By default, "All Nets" under the Nets tab should be checked. Under the Report tab, select "Generate PEX report" and "View report after PEX finishes". Under SVDB, make sure that "Start RVE after PEX" is checked.
−
\+3 (_net0 _net1) capacitor c=1.29997e-16 m=1
+
 
−
  \+2 (_net0 Z) capacitor c=2.87838e-17 m=1
+
One common error is that the pins are connected to the text layer and not the metal1 layer. You can't pass PEX unless all pins are set to metal1. Highlight the pin and press Q to see which layer the pin is connected to.
−
  \+0 (Z A _net1 _net1) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 \
+
 
−
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
+
After this, there are a few files that were created, namely .netlist, .pex, and .pxi
 +
 
 +
The .pex, containing the parasitic elements for each subcircuit looks something like:
 +
 
 +
  * File: invx1.pex.netlist.pex
 +
  * Created: Thu Oct  1 14:51:55 2009
 +
  * Program "Calibre xRC"
 +
* Version "v2008.3_16.12"
 +
*
 +
.subckt PM_SIMPLE_INV%Z 1 2 5 8
 +
c19 8 0 0.00519381f
 +
c20 5 0 0.0126473f
 +
c21 1 0 0.0438069f
 +
r22 8 9 102.4
 +
r23 3 8 0.0146822
 +
r24 3 5 0.866071
 +
r25 2 9 1.98769
 +
r26 1 9 2.95231
 +
.ends
 +
 
 +
 
 +
The actual netlist ("invx1.pex.netlist") with only the transistors is the .netlist file and looks like:
 +
 
 +
  * File: invx1.pex.netlist
 +
  * Created: Thu Oct  1 14:51:55 2009
 +
  * Program "Calibre xRC"
 +
  * Version "v2008.3_16.12"
 +
  *
 +
.include "simple_inv.pex.netlist.pex"
 +
.subckt simple_inv  Z A GND! VDD!
 +
*
 +
* VDD!  VDD!
 +
* GND!  GND!
 +
* A    A
 +
* Z    Z
 +
MM0@2 N_Z_MM0@2_d N_A_MM0@2_g N_GND!_MM0@2_s N_GND!_MM0@2_b NMOS_VTG L=5e-08
 +
+ W=1.8e-07 AD=2.52e-14 AS=1.89e-14 PD=6.4e-07 PS=5.7e-07
 +
  MM0 N_Z_MM0@2_d N_A_MM0_g N_GND!_MM0_s N_GND!_MM0@2_b NMOS_VTG L=5e-08 W=1.8e-07
 +
  + AD=2.52e-14 AS=1.89e-14 PD=6.4e-07 PS=5.7e-07
 +
  MM2@2 N_Z_MM2@2_d N_A_MM2@2_g N_VDD!_MM2@2_s N_VDD!_MM2@2_b PMOS_VTG L=5e-08
 +
  + W=3.6e-07 AD=5.04e-14 AS=3.78e-14 PD=1e-06 PS=9.3e-07
 +
MM2 N_Z_MM2@2_d N_A_MM2_g N_VDD!_MM2_s N_VDD!_MM2@2_b PMOS_VTG L=5e-08 W=3.6e-07
 +
+ AD=5.04e-14 AS=3.78e-14 PD=1e-06 PS=9.3e-07
 +
*
 +
.include "simple_inv.pex.netlist.SIMPLE_INV.pxi"
 +
*
 +
.ends
 +
 
 +
 
 +
The .pxi file ("invx1.pex.netlist.INVX1.pxi") contains the connections between the parasitics and the transistors. It looks like this:
 +
 
 +
* File: invx1.pex.netlist.INVX1.pxi
 +
* Created: Thu Oct  1 14:51:55 2009
 +
x_PM_SIMPLE_INV%Z N_Z_MM0@2_d N_Z_MM2@2_d Z N_Z_c_2_p PM_SIMPLE_INV%Z
 +
x_PM_SIMPLE_INV%A N_A_MM0@2_g N_A_MM2@2_g N_A_c_22_n N_A_c_28_p N_A_MM0_g
 +
+ N_A_MM2_g A N_A_c_26_n PM_SIMPLE_INV%A
 +
x_PM_SIMPLE_INV%GND! N_GND!_MM0@2_s N_GND!_MM0_s N_GND!_MM0@2_b N_GND!_c_44_n
 +
+ GND! PM_SIMPLE_INV%GND!
 +
x_PM_SIMPLE_INV%VDD! N_VDD!_MM2@2_s N_VDD!_MM2_s N_VDD!_MM2@2_b N_VDD!_c_57_n
 +
+ VDD! PM_SIMPLE_INV%VDD!
 +
cc_1 N_Z_MM0@2_d N_A_MM0@2_g 0.0107699f
 +
cc_2 N_Z_c_2_p N_A_MM0@2_g 0.0014234f
 +
cc_3 N_Z_MM0@2_d N_A_c_22_n 0.00106391f
 +
cc_4 N_Z_MM0@2_d N_A_MM0_g 0.0122772f
 +
 
 +
 
 +
If the above simulation gets too slow, you can run without resistive parasitics but with less accuracy. To do this, change the extraction type to "'''C+CC'''" instead of "'''R+C+CC'''".
 +
 
 +
Now, you are ready to run a back-annotated simulation.
 +
 
 +
=== Back-Annotated Simulation ===
 +
 
 +
To run simulations, copy the .pex, .pxi and .netlist file to your prior '''Hspice simulation directory'''.
 +
 
 +
Open the file named '''input.ckt''' located inside your ''Hspice simulation directory/hspiceD/schematic/netlist''.
 +
 
 +
Using "*" comment ONLY the lines starting with M (lines containing transistors)
 +
Type the following lines
 +
.include "invx1.pex.netlist"
 +
X1 Z A VDD! GND! invx1
 +
The first line includes the recently extracted netlist.
 +
 
 +
The second line is an instance invoking the cell you have recently designed and extracted.
 +
 
 +
The first field '''X1''' is called the instance name.
 +
 
 +
The last field '''invx1''' is the cell name you want to invoke.
 +
 
 +
The fields between these two are the list of inputs, outputs and supply interfaces. Make sure the order of these matches your .pex.netlist!
 +
 
 +
Open '''si.env''' file located inside your ''Hspice simulation directory/hspiceD/schematic/netlist'' and delete the lines containing '''simNetlistHier'''. Save '''si.env'''
 +
 
 +
The middle of your '''input.ckt''' file should resemble something like this:
  
−
Find out what vdd! and gnd! are called in layout by looking at the body terminals of a PMOS and NMOS. They should all be hooked together or else your layout is not complete. In my case, it was _net0 for vdd and _net1 for gnd. Then, hook these up to vdd or gnd as shown here along with your normal stimulus:
+
.INCLUDE "/projects/cmpe122/techfiles/FreePDK45-1.4/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTG.inc"
 +
.INCLUDE "/projects/cmpe122/techfiles/FreePDK45-1.4/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTG.inc"
 +
 +
** Library name: spring_lib
 +
** Cell name: invx1
 +
** View name: schematic
 +
*m0 z a 0 0 NMOS_VTG AD=25.2e-15 AS=37.8e-15 PD=280e-9 PS=780e-9 L=50e-9 W=180e-9 M=2
 +
*m2 z a vdd! vdd! PMOS_VTG AD=50.4e-15 AS=75.6e-15 PD=280e-9 PS=1.14e-6 L=50e-9 W=360e-9 M=2
 +
.include "invx1.pex.netlist"
 +
X1 Z A GND! VDD! invx1
 +
.include "/projects/cmpe122/users/rsankara/hspice_simul/invx1/hspiceD/schematic/netlist/stimuli/stimulus.sp"
 +
.END
  
−
// Spectre Source Statements
+
Make sure, your '''input.ckt''' already has ''.include for the models, and .END at the end of the file''
−
v0a (vdd _net0) resistor r=0
+
−
v1a (gnd _net1) resistor r=0
+
−
v0 (vdd vdd!) resistor r=0
+
−
v1 (gnd gnd!) resistor r=0
+
−
vdd (vdd 0) vsource dc=1.8
+
−
gnd (gnd 0) vsource dc=0
+
−
vin (A 0) vsource type=pulse val0=0 val1=1 period=100n delay=10n rise=0.1n fall=0.1n width=50n
+
  
−
Re-run your simulation and you should see the same behavior as the schematic-only simulation, but with different delays. If not, there is an error in your setup (assuming that LVS passed)!
+
On the ADE window, click '''Simulation->Run'''. This will now simulate the post extraction netlist.

Latest revision as of 02:01, 26 April 2014

The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. Spectre (or hSpice) will by default use the gate area (L and W) to estimate the gate capacitance, but additional poly is not considered. If you specified perimeters (ps, pd) and areas (as, ad) in the pcell form, it will include those estimates in simulation. However, it does not include any extra routing, contacts, diffusion, etc. In order to include these, you need to perform parasitic extraction and back-annotation. The extraction is similar to the device extraction you used to extract a netlist for LVS, but now it extracts parasitic resistances and capacitances too.

Your design must pass DRC and LVS to do this.

SCMOS Method

In order to include the extra interconnect parasitics, we must have done DRC, Extract, and LVS. There can be absolutely no errors or warnings in LVS. For example, even this doesn't allow back-annotation: 

termbad.out:
? Terminal A's type in the schematic: input, in the layout: inputOutput

You should see this at the bottom of your LVS report if you have no errors or warnings: 

Probe files from /mada/users/mrg/LayoutTest/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:


Probe files from /mada/users/mrg/LayoutTest/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:


Now, you are ready to back-annotate. However, in order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.

After re-running LVS, in the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.

Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Hspice simulation as normal. (In fact, you can just load the saved setup from the Hspice run directory.) Confirm that it works for the schematic. Then, go to Hspice->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:

Simulatebackannotated.jpg

Now it should have parasitics too!

To confirm this, look in your run directory after you run a back-annotated simulation and view the "netlist" file in the unix shell and you should see a bunch of transistors and capacitors. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter: 

// Library name: mylib
// Cell name: invx1
// View name: analog_extracted
\+1 (Z A vdd! vdd!) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat
\+5 (A 0) capacitor c=2.27853e-17 m=1
\+4 (Z 0) capacitor c=2.87838e-17 m=1
\+3 (vdd! 0) capacitor c=1.29997e-16 m=1
\+2 (vdd! Z) capacitor c=2.87838e-17 m=1
\+0 (Z A 0 0) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat

If you do not see the capacitors, then something is wrong.

FreePDK45 Method

This is very similar to LVS. Go to Calibre->Run PEX. You will need to specify a layer map like LVS again. Also, select the rule file as this: 

/projects/cmpe122/techfiles/FreePDK45/ncsu_basekit/techfile/calibre/calibrexRC.rul

Under the Input section, in the Layout tab, make sure that GDSII and "Export from layout viewer" are selected. Under the Netlist tab, make sure that SPICE and "Export from schematic viewer" are selected.

Under the Output section, most options should be left as default. Under Netlist, we want Hspice format and names from the SCHEMATIC. By default, "All Nets" under the Nets tab should be checked. Under the Report tab, select "Generate PEX report" and "View report after PEX finishes". Under SVDB, make sure that "Start RVE after PEX" is checked.

One common error is that the pins are connected to the text layer and not the metal1 layer. You can't pass PEX unless all pins are set to metal1. Highlight the pin and press Q to see which layer the pin is connected to.

After this, there are a few files that were created, namely .netlist, .pex, and .pxi

The .pex, containing the parasitic elements for each subcircuit looks something like: 

* File: invx1.pex.netlist.pex
* Created: Thu Oct  1 14:51:55 2009
* Program "Calibre xRC"
* Version "v2008.3_16.12"
*
.subckt PM_SIMPLE_INV%Z 1 2 5 8
c19 8 0 0.00519381f
c20 5 0 0.0126473f
c21 1 0 0.0438069f
r22 8 9 102.4
r23 3 8 0.0146822
r24 3 5 0.866071
r25 2 9 1.98769
r26 1 9 2.95231
.ends


The actual netlist ("invx1.pex.netlist") with only the transistors is the .netlist file and looks like: 

 * File: invx1.pex.netlist
 * Created: Thu Oct  1 14:51:55 2009
 * Program "Calibre xRC"
 * Version "v2008.3_16.12"
 * 
.include "simple_inv.pex.netlist.pex"
.subckt simple_inv  Z A GND! VDD!
*
* VDD!  VDD!
* GND!  GND!
* A     A
* Z     Z
MM0@2 N_Z_MM0@2_d N_A_MM0@2_g N_GND!_MM0@2_s N_GND!_MM0@2_b NMOS_VTG L=5e-08
+ W=1.8e-07 AD=2.52e-14 AS=1.89e-14 PD=6.4e-07 PS=5.7e-07
MM0 N_Z_MM0@2_d N_A_MM0_g N_GND!_MM0_s N_GND!_MM0@2_b NMOS_VTG L=5e-08 W=1.8e-07
+ AD=2.52e-14 AS=1.89e-14 PD=6.4e-07 PS=5.7e-07
MM2@2 N_Z_MM2@2_d N_A_MM2@2_g N_VDD!_MM2@2_s N_VDD!_MM2@2_b PMOS_VTG L=5e-08
+ W=3.6e-07 AD=5.04e-14 AS=3.78e-14 PD=1e-06 PS=9.3e-07
MM2 N_Z_MM2@2_d N_A_MM2_g N_VDD!_MM2_s N_VDD!_MM2@2_b PMOS_VTG L=5e-08 W=3.6e-07
+ AD=5.04e-14 AS=3.78e-14 PD=1e-06 PS=9.3e-07
*
.include "simple_inv.pex.netlist.SIMPLE_INV.pxi"
*
.ends


The .pxi file ("invx1.pex.netlist.INVX1.pxi") contains the connections between the parasitics and the transistors. It looks like this: 

* File: invx1.pex.netlist.INVX1.pxi
* Created: Thu Oct  1 14:51:55 2009
x_PM_SIMPLE_INV%Z N_Z_MM0@2_d N_Z_MM2@2_d Z N_Z_c_2_p PM_SIMPLE_INV%Z
x_PM_SIMPLE_INV%A N_A_MM0@2_g N_A_MM2@2_g N_A_c_22_n N_A_c_28_p N_A_MM0_g
+ N_A_MM2_g A N_A_c_26_n PM_SIMPLE_INV%A
x_PM_SIMPLE_INV%GND! N_GND!_MM0@2_s N_GND!_MM0_s N_GND!_MM0@2_b N_GND!_c_44_n
+ GND! PM_SIMPLE_INV%GND!
x_PM_SIMPLE_INV%VDD! N_VDD!_MM2@2_s N_VDD!_MM2_s N_VDD!_MM2@2_b N_VDD!_c_57_n
+ VDD! PM_SIMPLE_INV%VDD!
cc_1 N_Z_MM0@2_d N_A_MM0@2_g 0.0107699f
cc_2 N_Z_c_2_p N_A_MM0@2_g 0.0014234f
cc_3 N_Z_MM0@2_d N_A_c_22_n 0.00106391f
cc_4 N_Z_MM0@2_d N_A_MM0_g 0.0122772f


If the above simulation gets too slow, you can run without resistive parasitics but with less accuracy. To do this, change the extraction type to "C+CC" instead of "R+C+CC".

Now, you are ready to run a back-annotated simulation.

Back-Annotated Simulation

To run simulations, copy the .pex, .pxi and .netlist file to your prior Hspice simulation directory.

Open the file named input.ckt located inside your Hspice simulation directory/hspiceD/schematic/netlist.

Using "*" comment ONLY the lines starting with M (lines containing transistors) Type the following lines 

.include "invx1.pex.netlist"
X1 Z A VDD! GND! invx1

The first line includes the recently extracted netlist.

The second line is an instance invoking the cell you have recently designed and extracted.

The first field X1 is called the instance name.

The last field invx1 is the cell name you want to invoke.

The fields between these two are the list of inputs, outputs and supply interfaces. Make sure the order of these matches your .pex.netlist!

Open si.env file located inside your Hspice simulation directory/hspiceD/schematic/netlist and delete the lines containing simNetlistHier. Save si.env

The middle of your input.ckt file should resemble something like this: 

.INCLUDE "/projects/cmpe122/techfiles/FreePDK45-1.4/ncsu_basekit/models/hspice/tran_models/models_nom/PMOS_VTG.inc"
.INCLUDE "/projects/cmpe122/techfiles/FreePDK45-1.4/ncsu_basekit/models/hspice/tran_models/models_nom/NMOS_VTG.inc"

** Library name: spring_lib
** Cell name: invx1
** View name: schematic
*m0 z a 0 0 NMOS_VTG AD=25.2e-15 AS=37.8e-15 PD=280e-9 PS=780e-9 L=50e-9 W=180e-9 M=2
*m2 z a vdd! vdd! PMOS_VTG AD=50.4e-15 AS=75.6e-15 PD=280e-9 PS=1.14e-6 L=50e-9 W=360e-9 M=2
.include "invx1.pex.netlist"
X1 Z A GND! VDD! invx1
.include "/projects/cmpe122/users/rsankara/hspice_simul/invx1/hspiceD/schematic/netlist/stimuli/stimulus.sp"
.END

Make sure, your input.ckt already has .include for the models, and .END at the end of the file

On the ADE window, click Simulation->Run. This will now simulate the post extraction netlist.

Retrieved from "https://vlsiwiki.soe.ucsc.edu/index.php?title=Back_Annotation&oldid=5137"