Difference between revisions of "Leon3"
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(1) Command Used: make distclean && time `make synplify && make quartus-synp` | (1) Command Used: make distclean && time `make synplify && make quartus-synp` | ||
| + | |||
| + | AMBA BUS Notes: (From 1999 ARM ihi 0011A Document) | ||
| + | |||
| + | AMBA signal names | ||
| + | All AMBA signals are named such that the first letter of the name indicates which bus | ||
| + | the signal is associated with. A lower case n in the signal name indicates that the signal | ||
| + | is active LOW, otherwise signal names are always all upper case. | ||
| + | Test signals have a prefix T regardless of the bus type. More information on test signals | ||
| + | can be found in Chapter 6 AMBA Test Methodology. | ||
Revision as of 09:56, 11 August 2009
Tom Golubev's Leon3 Based Logic Analyzer
Using NIOSII Cyclone dev board
Leon3 grlib-gpl-1.0.20-b3403
FPGA Usage (1): Configuration: LUT Usage (%) Mem Usage (%) System MHz (1) Default: noFpu, noMMU 56 % 36 % 135.9 (2) noFPU, MMU 65 % 37 % 134.8
(1) Command Used: make distclean && time `make synplify && make quartus-synp`
AMBA BUS Notes: (From 1999 ARM ihi 0011A Document)
AMBA signal names
All AMBA signals are named such that the first letter of the name indicates which bus
the signal is associated with. A lower case n in the signal name indicates that the signal
is active LOW, otherwise signal names are always all upper case.
Test signals have a prefix T regardless of the bus type. More information on test signals
can be found in Chapter 6 AMBA Test Methodology.
