Difference between revisions of "Leon3"
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(1) Command Used: make distclean && time `make synplify && make quartus-synp` | (1) Command Used: make distclean && time `make synplify && make quartus-synp` | ||
| + | |||
| + | ==Design Questions== | ||
| + | |||
| + | 1) How easy is it to have mixed VHDL / Verilog Design using Synplify? | ||
| + | |||
| + | 2) How much throughput is needed? | ||
| + | |||
| + | 3) Which bus to use? AHB, APB? or tightly couple to proc (difficult) | ||
==AMBA BUS Notes:== (From 1999 ARM ihi 0011A Document) | ==AMBA BUS Notes:== (From 1999 ARM ihi 0011A Document) | ||
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Nios II / Leon2 Comparison CoSCPU.pdf | Nios II / Leon2 Comparison CoSCPU.pdf | ||
Leon2 / MicroBlaze / OpenRISC1200 Comparison Evaluation_of_synthesizable_CPU_cores.pdf | Leon2 / MicroBlaze / OpenRISC1200 Comparison Evaluation_of_synthesizable_CPU_cores.pdf | ||
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==Sources== | ==Sources== | ||
Revision as of 22:23, 11 August 2009
Tom Golubev's Leon3 Based Logic Analyzer
Using NIOSII Cyclone dev board
Leon3 grlib-gpl-1.0.20-b3403
FPGA Usage (1): EP1C20F400C7 Configuration: LUT Usage (%) Mem Usage (%) System MHz (1) Default: noFpu, noMMU 56 % 36 % 135.9 (2) noFPU, MMU 65 % 37 % 134.8 (3) Bare 38 % 18 % 126.1
(1) Command Used: make distclean && time `make synplify && make quartus-synp`
Design Questions
1) How easy is it to have mixed VHDL / Verilog Design using Synplify?
2) How much throughput is needed?
3) Which bus to use? AHB, APB? or tightly couple to proc (difficult)
==AMBA BUS Notes:== (From 1999 ARM ihi 0011A Document)
AMBA signal names
All AMBA signals are named such that the first letter of the name indicates which bus
the signal is associated with. A lower case n in the signal name indicates that the signal
is active LOW, otherwise signal names are always all upper case.
Test signals have a prefix T regardless of the bus type. More information on test signals
can be found in Chapter 6 AMBA Test Methodology.
Important Sources / Documents: Nios II / Leon2 Comparison CoSCPU.pdf Leon2 / MicroBlaze / OpenRISC1200 Comparison Evaluation_of_synthesizable_CPU_cores.pdf
Sources
(ASAP 2006). S. Tillich and J. Großsch¨adl. Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. In Cryptographic Hardware and Embedded Systems — CHES 2006, vol. 4249 of Lecture Notes in Computer Science, pp. 270–284. Springer Verlag, 2006.
A. Hodjat, I. Verbauwhede : Interfacing a high speed crypto accelerator to an embedded CPU. In: Proceedings of the 38th Asilomar Conference on Signals, Systems, and Computers, vol. 1, pp. 488–492. IEEE, New York (2004) P. Schaumont, K. Sakiyama, A. Hodjat, and I. Verbauwhede.
Embedded Software Integration for Coarse-Grain Reconfigurable Systems. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), pp. 137–142, IEEE CS Press, 2004.
An AES Tightly Coupled Hardware Accelerator in an FPGA-based Embedded Processor Core
