Difference between revisions of "Full-Custom FAQ"

Revision as of 23:48, 1 October 2007

I'm confused about the layers...

The "active" layer determines the source-gate-drain locations of both NMOS and PMOS devices. The opposite of active determines where the field oxide is grown. The overlap of the active layer and the poly layer determines where the gate oxide is grown.

The "P-select" layer covers the PMOS device with photoresist so that the NMOS can be ion implanted with n-type ions to form the doped source and drain.

The "N-select" layer covers the NMOS device with photoresist so that the PMOS can be ion implanted with p-type ions to form the doped source and drain.

Some processes (i.e. not MOSIS) do not have the select layers and instead have separate n and p active layers. The select layer is then derived from this. (This means there are only 2 instead of 3 drawn layers in these processes.)

Also note that the video today showed an additional implant from what we described in class. The implant was before the source and drain implant and before poly. It is the threshold implant which adjusts the characteristics of the transistor. We will discuss this more on monday when I get into the electrical characteristics of MOS devices.

My LVS doesn't match vdd! and/or gnd!

This has many possibilities. The most common are:

1. You didn't make an inputOutput pin in the layout.
2. vdd and vcc are not the same components. The "body" (well) of the transistors in our library (nmos/pmos) are assumed to automatically connect to gnd! and vdd!, respectively. If you use vcc instead of vdd, this will cause a floating net problem and LVS won't run. You can intentionally change this by using the nmos4/pmos4 devices that let you explicitly connect the body, but that should be unnecessary for this class.

Why does my extracted netlist seem disconnected?

Your designs WILL NOT PASS LVS if you use Create->Via. It will appear that the nets are disconnected if you try to highlight them in the extracted view. For example, your first level inverter output should connect to all the other FO4 poly gates. If you select the metal net in the extracted view and it does not highlight all the poly gates, you have this problem!

I get an error from DRC that an "edge is not on grid". Why?

I'm not sure how you made the shape, but shapes are required to be on a grid of 0.045. There is an option under the Options->Display Options to specify the x- and y-snap. Make sure this is set correctly, delete the offending shape, and redraw it.

When I run LVS, I'm getting the following error: Can't find/read file '.../LVS/si.out

This is the output of the LVS program. If it did not run, it didn't create this so when you try to view it by clicking the "Output" button, it will give this error. If this is the case, it should open another window. Click on the "Log" button... to see why the program didn't run.

The likely reasons are: 1) You didn't Check and Save your schematic 2) You modified your layout after running extraction.

My icfb crashed and I get a problem with a lock file now... what do I do?

Delete the obsolete lock files from a previous session. The lock file names are determined by adding ".cdslck" to the name of the file in the error message.

So for the file /home/aa/users/jdoe/CDS.log.1 the lock file is /home/aa/users/jdoe/CDS.log.1.cdslck

You can delete it with the UNIX command rm.

How do I draw a large numer of pins? On a bus, for example.

There's a neat feature that is pretty to use called auto pin. When you Create->Pin.... input a bus name like A<0>. Check the box "Keep First Name". Do NOT select Auto Pin; leave it as Rectangle. Change the Y pitch to specify that they should be spaced out horizontally.

Select the layer you want to draw the pin on in the LSW. Draw a single rectangle that is the size you want all the pins to be. Place the label on the pin. After the click for the label, all the other pins will appear.

LVS fails to run with an error: "Cannot find switch master cell instance M0 in cellView (inv schematic) from viewlist 'lvs shematic gate_sch cmos_sch' in library '...'." Why?

You are not sourcing the class setup and missed this configuration variable:

export CDS_Netlisting_Mode=Analog