Difference between revisions of "Analog/Mixed Signal"

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Verilog-A

The following sections provide an overview to Verilog-A,

What is Verilog-A

Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project. Unfortunately, there was considerable delay between the first Verilog-A LRM and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera. Hence, the original goal of a single language standard is still to be achieved Brief List of Functions Available in Verilog-A

Taken from http://en.wikipedia.org/wiki/Verilog-A

Coding Examples

-Cadence AHDL Library
        -Sample Modules

What simulators can run it

-Link to Ultrasim -Link to Spectre

Resources

-Link of online resources

Verilog-AMS

Verilog-AMS