Difference between revisions of "VPI DEBUG"
Tom Golubev (Talk | contribs) (Created page with '==Retrieved on 11/25/09 from http://bbs.dicder.com/archiver/index.php?tid-499.html== <strong>5life</strong> 发表于 2006-3-13 04:41 PM</p> <h3>How to Debug PLI, DPI, and Dire…') |
Tom Golubev (Talk | contribs) (→Retrieved on 11/25/09 from http://bbs.dicder.com/archiver/index.php?tid-499.html) |
||
Line 1: | Line 1: | ||
− | ==Retrieved on 11/25/09 from http://bbs.dicder.com/archiver/index.php?tid-499.html== | + | ==Retrieved and Adapted on 11/25/09 from http://bbs.dicder.com/archiver/index.php?tid-499.html== |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | + | <h3>How to Debug PLI, VPI, and DirectC applications using gdb</h3>INTRODUCTION:<br> | |
− | + | <br> | |
− | + | You can add new functionality to a Verilog simulator such as VCS by<br> | |
− | + | linking in your C code. You can also call C code from OpenVera<br> | |
− | + | testbenches. Perhaps you have a C model, made of routines in the file<br> | |
− | + | ||
− | + | model.c, and invoked with the Verilog system task $model. The C code<br> | |
− | <br | + | is known as the application, and will consist of one or more routines.<br> |
− | + | The connection between the application and the simulator is the PLI,<br> | |
− | + | the Programming Language Interface. The application will be called<br> | |
− | + | during simulation either directly, when VCS executes the system task<br> | |
+ | for the application ($model), or asynchronously when VCS is doing an<br> | ||
− | <br>< | + | activity such as initialization or shutdown.<br> |
− | + | <br> | |
− | < | + | Alternately, you want to call a C routine such as log2() directly<br> |
− | + | using VCS DirectC interface, or the new DPI (Direct Procedural<br> | |
− | + | Interface) that is part of SystemVerilog. Only the linking differs.<br> | |
− | <br> | + | <br><br> |
− | + | COMPILING:<br> | |
− | You must do several steps to debug the C application. | + | <br> |
− | be compiled for debug, linked with the Verilog code, the simulator | + | You must do several steps to debug the C application. The C code must<br> |
− | + | be compiled for debug, linked with the Verilog code, the simulator<br> | |
− | must be started with the debugger, and a breakpoint needs to be added | + | must be started with the debugger, and a breakpoint needs to be added<br> |
− | in the application. | + | in the application. This guide only covers using the GNU gcc compiler<br> |
− | and the matching gdb debugger. | + | and the matching gdb debugger. Other tools will have a similar flow.<br> |
− | <br | + | <br> |
− | First, the C code must be compiled with -g so that its debug symbols, such | + | First, the C code must be compiled with -g so that its debug symbols, such<br> |
− | as variables and routine names, will be visible at run-time.<br | + | as variables and routine names, will be visible at run-time.<br> |
− | + | <br> | |
− | + | gcc -g -o model.c -I${VCS_HOME}/include<br> | |
− | <br | + | <br> |
− | The -o switch tells gcc to create object code (model.o) and not an | + | The -o switch tells gcc to create object code (model.o) and not an<br> |
− | executable. | + | executable. The -I switch points to the VCS include files that define<br> |
− | constants and the PLI routine names. | + | constants and the PLI routine names.<br> |
− | + | <br> | |
− | Next link the C code into your simulation:<br | + | Next link the C code into your simulation:<br> |
− | <br | + | <br> |
− | + | vcs design.v -P model.tab model.o<br> | |
− | <br | + | <br> |
− | The Verilog code is in design.v, your C code is in model.o, and<br | + | The Verilog code is in design.v, your C code is in model.o, and<br> |
− | model.tab tells VCS which C routines to call when $model is used in | + | model.tab tells VCS which C routines to call when $model is used in<br> |
− | the Verilog. | + | the Verilog. This produces the executable simv.<br> |
− | + | <br> | |
− | Alternately, you can compile the Verilog and C code together. | + | Alternately, you can compile the Verilog and C code together.;Use the<br> |
− | VCS -CFLAGS option to pass flags to the C compiler: | + | VCS -CFLAGS option to pass flags to the C compiler: |
− | model.tab model.c \ -CFLAGS | + | vcs design.v -P model.tab model.c \ -CFLAGS "-g -I${VCS_HOME}/include" <br> |
− | + | <br> | |
− | + | If you are using DirectC, you don't need a table file:<br> | |
− | + | <br> | |
− | + | ||
− | If you are using DirectC, you don | + | |
− | + | ||
− | <br | + | |
− | + | vcs +dc design.v model.o<br> | |
− | <br> | + | <br> |
− | + | <br> | |
− | + | <br> | |
− | + | RUNNING THE DEBUGGER<br> | |
− | + | <br> | |
− | <br | + | |
− | RUNNING THE DEBUGGER | + | |
− | + | ||
− | Now you are ready to roll! | + | Now you are ready to roll! Start the debugger and tell it which<br> |
− | executable to use: | + | executable to use:<br> |
− | + | <br> | |
− | + | gdb simv<br> | |
− | + | <br> | |
− | + | ||
− | + | (gdb)<br> | |
− | + | Here you can set a breakpoint on a C routine:<br> | |
− | Here you can set a breakpoint on a C routine: | + | <br> |
− | + | (gdb) br model_call<br> | |
− | + | ||
− | + | ||
− | + | Breakpoint 1 at 0x8050ba6: file model.c, line 12.<br> | |
− | + | <br> | |
− | Now run the simulation, specifying the command line switches to use with simv:<br | + | Now run the simulation, specifying the command line switches to use with simv:<br> |
− | <br | + | <br> |
− | + | (gdb) run -l simv.log<br> | |
− | + | Starting program: /disk/user/simv<br> | |
− | + | Chronologic VCS Simulator copyright 1991-2004 | |
− | + | <br> | |
− | + | <br> | |
− | + | Breakpoint 1, model_call() at model.c:12<br> | |
− | + | ||
− | + | (gdb)<br> | |
− | + | <br> | |
− | Now you can step through the code (step and next), print variable | + | Now you can step through the code (step and next), print variable<br> |
− | values (print and x), look at the call stack (bt) and other debugger<br | + | values (print and x), look at the call stack (bt) and other debugger<br> |
− | tricks. | + | tricks. If you run gdb inside Emacs (M-X gdb) you can see the source<br> |
− | code in one window while the debugger runs in the other. | + | code in one window while the debugger runs in the other.<br> |
− | <br | + | <br> |
− | This guide only shows how to debug code linked directly with VCS, not | + | This guide only shows how to debug code linked directly with VCS, not<br> |
− | shareable code. | + | shareable code. Shareable code is only loaded into memory when<br> |
− | + | needed, not at the start of execution. So you can not set a<br> | |
− | + | ||
− | needed, not at the start of execution. | + | |
− | + | ||
− | breakpoint on your code when gdb loads the executable as your code is | + | breakpoint on your code when gdb loads the executable as your code is<br> |
not in memory yet. | not in memory yet. |
Revision as of 23:37, 25 November 2009
Retrieved and Adapted on 11/25/09 from http://bbs.dicder.com/archiver/index.php?tid-499.html
How to Debug PLI, VPI, and DirectC applications using gdb
INTRODUCTION:
You can add new functionality to a Verilog simulator such as VCS by
linking in your C code. You can also call C code from OpenVera
testbenches. Perhaps you have a C model, made of routines in the file
model.c, and invoked with the Verilog system task $model. The C code
is known as the application, and will consist of one or more routines.
The connection between the application and the simulator is the PLI,
the Programming Language Interface. The application will be called
during simulation either directly, when VCS executes the system task
for the application ($model), or asynchronously when VCS is doing an
activity such as initialization or shutdown.
Alternately, you want to call a C routine such as log2() directly
using VCS DirectC interface, or the new DPI (Direct Procedural
Interface) that is part of SystemVerilog. Only the linking differs.
COMPILING:
You must do several steps to debug the C application. The C code must
be compiled for debug, linked with the Verilog code, the simulator
must be started with the debugger, and a breakpoint needs to be added
in the application. This guide only covers using the GNU gcc compiler
and the matching gdb debugger. Other tools will have a similar flow.
First, the C code must be compiled with -g so that its debug symbols, such
as variables and routine names, will be visible at run-time.
gcc -g -o model.c -I${VCS_HOME}/include
The -o switch tells gcc to create object code (model.o) and not an
executable. The -I switch points to the VCS include files that define
constants and the PLI routine names.
Next link the C code into your simulation:
vcs design.v -P model.tab model.o
The Verilog code is in design.v, your C code is in model.o, and
model.tab tells VCS which C routines to call when $model is used in
the Verilog. This produces the executable simv.
Alternately, you can compile the Verilog and C code together.;Use the
VCS -CFLAGS option to pass flags to the C compiler:
vcs design.v -P model.tab model.c \ -CFLAGS "-g -I${VCS_HOME}/include"
If you are using DirectC, you don't need a table file:
vcs +dc design.v model.o
RUNNING THE DEBUGGER
Now you are ready to roll! Start the debugger and tell it which
executable to use:
gdb simv
(gdb)
Here you can set a breakpoint on a C routine:
(gdb) br model_call
Breakpoint 1 at 0x8050ba6: file model.c, line 12.
Now run the simulation, specifying the command line switches to use with simv:
(gdb) run -l simv.log
Starting program: /disk/user/simv
Chronologic VCS Simulator copyright 1991-2004
Breakpoint 1, model_call() at model.c:12
(gdb)
Now you can step through the code (step and next), print variable
values (print and x), look at the call stack (bt) and other debugger
tricks. If you run gdb inside Emacs (M-X gdb) you can see the source
code in one window while the debugger runs in the other.
This guide only shows how to debug code linked directly with VCS, not
shareable code. Shareable code is only loaded into memory when
needed, not at the start of execution. So you can not set a
breakpoint on your code when gdb loads the executable as your code is
not in memory yet.