Difference between revisions of "280G S12"
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This quarter, we are going to focus on sub-threshold circuits. Here are some possible papers to cover: | This quarter, we are going to focus on sub-threshold circuits. Here are some possible papers to cover: | ||
− | * http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1644879 | + | * Static noise margin variation for sub-threshold SRAM in 65-nm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1644879 |
− | * http://people.virginia.edu/~bhc2b/papers/Calhoun_ISSCC06.pdf | + | * A 256kb Sub-threshold SRAM in 65nm CMOS http://people.virginia.edu/~bhc2b/papers/Calhoun_ISSCC06.pdf |
− | * http://dl.acm.org/citation.cfm?id=1165578 | + | * Variation-driven device sizing for minimum energy sub-threshold circuits http://dl.acm.org/citation.cfm?id=1165578 |
− | * http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4242400 | + | * A Sub-200mV 6T SRAM in 0.13μm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4242400 |
− | * http://dl.acm.org/citation.cfm?id=996798 | + | * Theoretical and practical limits of dynamic voltage scaling http://dl.acm.org/citation.cfm?id=996798 |
* The sub-vth flop paper Raj showed me? | * The sub-vth flop paper Raj showed me? | ||
− | * http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf | + | * A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf |
Revision as of 19:24, 14 March 2012
This quarter, we are going to focus on sub-threshold circuits. Here are some possible papers to cover:
- Static noise margin variation for sub-threshold SRAM in 65-nm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1644879
- A 256kb Sub-threshold SRAM in 65nm CMOS http://people.virginia.edu/~bhc2b/papers/Calhoun_ISSCC06.pdf
- Variation-driven device sizing for minimum energy sub-threshold circuits http://dl.acm.org/citation.cfm?id=1165578
- A Sub-200mV 6T SRAM in 0.13μm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4242400
- Theoretical and practical limits of dynamic voltage scaling http://dl.acm.org/citation.cfm?id=996798
- The sub-vth flop paper Raj showed me?
- A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf