Difference between revisions of "280G S12"

Revision as of 20:54, 13 April 2012

This quarter, we are going to focus on sub-threshold circuits.

Here are some possible papers to cover:

Theory/General:

• Theoretical and practical limits of dynamic voltage scaling http://dl.acm.org/citation.cfm?id=996798
• Variation-driven device sizing for minimum energy sub-threshold circuits http://dl.acm.org/citation.cfm?id=1165578
• Optimal Supply and Threshold Voltage Scaling for Sub-threshold CMOS Circuits by Alice Wang, Anantha Chandrakasan, Stephen Kosonocky
• A Variation Tolerant Sub-threshold Design Approach by Nikhil Jayakumar and Sunil Khatri
• Technology Flavor Selection and Adaptive Techniques for Timing Constrined 45nm Sub-threshold Circuits by David Bol and others
• A 180mv Subthreshold FFT processor using a Minimum Energy Design Methodology by Alice Wang and Anantha Chandrakasan
• Digital Computation in Subthreshold Region for Ultra Low Power Operation by Sumeet Kumar Gupta and others
• Technologies for Ultradynamic Voltage Scaling by Anantha Chandrakasan and others
• Flexible Circuits and Architectures for Ultra Low Power by Benton Calhoun and others
• Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS by Benton Calhoun and others
• Energy Efficient Near-Threshold Chip Multi-Processing by Bo Zhai and others
• Sub-threshold Design: The challenges of minimizing circuit energy by Benton Calhoun and others
• Design Considerations for Ultra Low Energy Wireless Microsensor Nodes by benton Calhoun and others
• Supply and Threshold Voltage Scaling for Low Power CMOS by Ricardo Gonzalez and others
• Nanometer Device Scaling in Subthreshold Logic and SRAM by Scott Hanson and others

Memories:

• Static noise margin variation for sub-threshold SRAM in 65-nm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1644879
• A 256kb Sub-threshold SRAM in 65nm CMOS http://people.virginia.edu/~bhc2b/papers/Calhoun_ISSCC06.pdf
• A Sub-200mV 6T SRAM in 0.13μm CMOS http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4242400

FPGAs:

• A Sub-Threshold FPGA with Low-Swing DualVDD Interconnect in 90nm CMOS http://rlpvlsi.ece.virginia.edu/sites/default/files/Ryan_CICC2010.pdf

Optimization:

• Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits by Benton Calhoun and others
• Device Sizing for Minimum Energy Operation in Subthreshold Circuits by Benton Calhoun and others

Variability/Modeling:

• Variability of Flip-Flop Timing at Sub-Threshold Voltages" by Niklas Lotze, Maurits Ortmanns, and Yiannos Manoli
• Exploring Variability and Performance in a Sub-200mv Processor by Scott Hanson and others