Difference between revisions of "280G F12"
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[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=912693&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DThe+design+and+analysis+of+the+clock+distribution+network+for+a+1.2GHz+alpha+microprocessor The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor] | [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=912693&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DThe+design+and+analysis+of+the+clock+distribution+network+for+a+1.2GHz+alpha+microprocessor The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor] | ||
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| + | '''Other:''' | ||
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| + | [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=929649&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DClock+distribution+networks+in+synchronous+digital+integrated+circuits Clock distribution networks in synchronous digital integrated circuits] | ||
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| + | [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=55696&contentType=Journals+%26+MagazinessearchWithin%3Dp_Authors%3A.QT.Fishburn%2C+J.P..QT.%26refinements%3D4294947175%26sortType%3Dasc_p_Publication_Year%26searchField%3DSearch_All Clock skew optimization] | ||
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| + | [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=503938&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3DPost-processing+of+clock+trees+via+wiresizing+and+buffering+for+robust+design Post-processing of clock trees via wiresizing and buffering for robust design] | ||
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| + | [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1560135&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DPractical+techniques+to+reduce+skew+and+its+variations+in+buffered+clock+networks Practical techniques to reduce skew and its variations in buffered clock networks] | ||
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| + | [http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=1167599&contentType=Conference+Publications&searchField%3DSearch_All%26queryText%3DGeneral+framework+for+removal+of+clock+network+pessimism General framework for removal of clock network pessimism] | ||
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| + | [http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.8567 Performance optimization of vlsi interconnect layout] | ||
Revision as of 22:00, 19 October 2012
This quarter, we will put a focus on resonant and non-traditional clocking. We will have two presenters each day -- about 30-40 min each. Please select papers on either distributed/monolithic LC, rotary clocking, or standing wave clocking or similar non-traditional clocking papers.
| Date | Presenter | Topic/Paper |
|---|---|---|
| 10/03/12 | Raj,Blake,Seokjoong | VLSI-SOC Dry Run ** Will need to start at 10:30am sharp |
| 10/10/12 | NONE (VLSI-SoC) | |
| 10/17/12 | NONE (Matt at NSF) | |
| 10/24/12 | Matt | How to review papers, Read the clock survey I wrote |
| 10/31/12 | Raj, Jeff | |
| 11/07/12 | NONE (Matt at ICCAD) | |
| 11/14/12 | Ben, Riadul | |
| 11/21/12 | Bin, Nihan | |
| 11/28/12 | Hany, Rafael | |
| 12/05/12 | Elnaz, Nihan |
Papers:
Uniform-phase uniform-amplitude resonant-load global clock distributions
Resonant clocking using distributed parasitic capacitance,
Jitter Characteristic in Charge Recovery Resonant Clock Distribution,
Design of resonant global clock distributions
Resonant-Clock Latch-Based Design
Variability:
Efficient coupled noise estimation for on-chip interconnects
Practical clock tree robustness signoff metrics
Process variation aware clock tree routing
SSTA:
Statistical timing analysis considering spatial correlations using a single PERT-like traversal
Statistical timing analysis using bounds and selective enumeration
First-order incremental block-based statistical timing analysis
Statistical timing analysis: From basic principles to state of the art
Statistical static timing analysis: A survey
Statistical clock skew analysis considering intra-die process variations
Statistical analysis of clock skew variation in H-tree structure
Implementation:
The clock distribution of the POWER4 microprocessor
A 5GHz duty-cycle correcting clock distribution network for the POWER6 microprocessor
Multi-GHz clocking scheme for Intel Pentium 4 microprocessor
Myth busters: Microprocessor clocking is from mars, asic’s clocking is from venus?
Clocking design and analysis for a 600-MHz Alpha microprocessor
A 300-MHz 64-b quad-issue CMOS RISC microprocessor
A 200-MHz 64-b dual-issue CMOS microprocessor
The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor
Other:
Clock distribution networks in synchronous digital integrated circuits
Post-processing of clock trees via wiresizing and buffering for robust design
Practical techniques to reduce skew and its variations in buffered clock networks
