Difference between revisions of "Back Annotation"

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(→‎FreePDK45 Method)
(→‎SCMOS Method)
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After re-running LVS, in the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.  
 
After re-running LVS, in the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.  
  
−
Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Spectre simulation as normal. (In fact, you can just load the saved setup from the spectre.run1 directory.) Confirm that it works for the schematic. Then, go to Spectre->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:
+
Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Hspice simulation as normal. (In fact, you can just load the saved setup from the Hspice run directory.) Confirm that it works for the schematic. Then, go to Hspice->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:
  
 
[[Image:simulatebackannotated.jpg|400px]]
 
[[Image:simulatebackannotated.jpg|400px]]
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If you do not see the capacitors, then something is wrong.
 
If you do not see the capacitors, then something is wrong.
−
 
  
 
== FreePDK45 Method ==
 
== FreePDK45 Method ==

Revision as of 21:46, 29 April 2013

The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. Spectre (or hSpice) will by default use the gate area (L and W) to estimate the gate capacitance, but additional poly is not considered. If you specified perimeters (ps, pd) and areas (as, ad) in the pcell form, it will include those estimates in simulation. However, it does not include any extra routing, contacts, diffusion, etc. In order to include these, you need to perform parasitic extraction and back-annotation. The extraction is similar to the device extraction you used to extract a netlist for LVS, but now it extracts parasitic resistances and capacitances too.

Your design must pass DRC and LVS to do this.

SCMOS Method

In order to include the extra interconnect parasitics, we must have done DRC, Extract, and LVS. There can be absolutely no errors or warnings in LVS. For example, even this doesn't allow back-annotation: 

termbad.out:
? Terminal A's type in the schematic: input, in the layout: inputOutput

You should see this at the bottom of your LVS report if you have no errors or warnings: 

Probe files from /mada/users/mrg/LayoutTest/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:


Probe files from /mada/users/mrg/LayoutTest/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:


Now, you are ready to back-annotate. However, in order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.

After re-running LVS, in the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.

Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Hspice simulation as normal. (In fact, you can just load the saved setup from the Hspice run directory.) Confirm that it works for the schematic. Then, go to Hspice->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:

Simulatebackannotated.jpg

Now it should have parasitics too!

To confirm this, look in your run directory (e.g. spectre.run1) after you run a back-annotated simulation and view the "netlist" file in the unix shell and you should see a bunch of transistors and capacitors. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter: 

// Library name: mylib
// Cell name: invx1
// View name: analog_extracted
\+1 (Z A vdd! vdd!) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat
\+5 (A 0) capacitor c=2.27853e-17 m=1
\+4 (Z 0) capacitor c=2.87838e-17 m=1
\+3 (vdd! 0) capacitor c=1.29997e-16 m=1
\+2 (vdd! Z) capacitor c=2.87838e-17 m=1
\+0 (Z A 0 0) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat

If you do not see the capacitors, then something is wrong.

FreePDK45 Method

This is very similar to LVS. Go to Calibre->Run PEX. You will need to specify a layer map like LVS again. Also, select the rule file as this: 

/mada/software/techfiles/FreePDK45/ncsu_basekit/techfile/calibre/calibrexRC.rul

Under the Input section, in the Layout tab, make sure that GDSII and "Export from layout viewer" are selected. Under the Netlist tab, make sure that SPICE and "Export from schematic viewer" are selected.

Under the Output section, most options should be left as default. Under Netlist, we want Hspice format and names from the SCHEMATIC. By default, "All Nets" under the Nets tab should be checked. Under the Report tab, select "Generate PEX report" and "View report after PEX finishes". Under SVDB, make sure that "Start RVE after PEX" is checked.

One common error is that the pins are connected to the text layer and not the metal1 layer. You can't pass PEX unless all pins are set to metal1. Highlight the pin and press Q to see which layer the pin is connected to.

After this, there are a few files that were created

  • The .pex file ("invx1.pex.netlist.pex") contains all of the parasitics in a hierarchical format:
// File: invx1.pex.netlist.pex
// Created: Thu Oct  1 14:51:55 2009
// Program "Calibre xRC"
// Version "v2008.3_16.12"
// Nominal Temperature: 27C
// Circuit Temperature: 27C
// 

subckt PM_INVX1\%A ( 2 6 10 17 )
c11 ( 17 0 ) capacitor c=0.00982231f
c12 ( 10 0 ) capacitor c=0.00443547f
c13 ( 6 0 ) capacitor c=0.0295338f
c14 ( 2 0 ) capacitor c=0.023213f
r15 ( 13 17 ) resistor r=6.448 
r16 ( 10 13 ) resistor r=89.3538 
r17 ( 5 17 ) resistor r=1.95 
r18 ( 5 6 ) resistor r=37.44 
r19 ( 1 17 ) resistor r=1.95 
r20 ( 1 2 ) resistor r=30.81 
ends PM_INVX1\%A 

subckt PM_INVX1\%Z ( 3 7 8 )
c8 ( 3 0 ) capacitor c=0.0253156f
r9 ( 7 8 ) resistor r=1.30077 
r10 ( 3 7 ) resistor r=1.43231 
ends PM_INVX1\%Z

etc.
  • The actual netlist ("NAND2.pex.netlist") with only the transistors is the .netlist file:
// File: invx1.pex.netlist
// Created: Thu Oct  1 14:51:55 2009
// Program "Calibre xRC"
// Version "v2008.3_16.12"
// 

include "invx1.pex.netlist.pex"
subckt invx1 (  )
// 
// GND!	GND!
// VDD!	VDD!
// Z	Z
// A	A
MM0 ( N_Z_MM0_d N_A_MM0_g N_GND!_MM0_s N_GND!_MM0_b ) NMOS_VTL l=5e-08 w=9e-08 \
 ad=9.45e-15 as=9.45e-15 pd=3.9e-07 ps=3.9e-07
MM1 ( N_Z_MM1_d N_A_MM1_g N_VDD!_MM1_s N_VDD!_MM1_b ) PMOS_VTL l=5e-08 \
 w=1.8e-07 ad=1.89e-14 as=1.89e-14 pd=5.7e-07 ps=5.7e-07
// 
include "invx1.pex.netlist.INVX1.pxi"
// 
ends INVX1
//  
//


  • The .pxi file ("invx1.pex.netlist.INVX1.pxi") contains the connections between the parasitics and the transistors. It looks like this:
// File: invx1.pex.netlist.INVX1.pxi
// Created: Thu Oct  1 14:51:55 2009
// 

x_PM_INVX1\%A ( N_A_MM0_g N_A_MM1_g A N_A_c_5_p )  PM_INVX1\%A
x_PM_INVX1\%Z ( N_Z_MM0_d Z N_Z_MM1_d )  PM_INVX1\%Z
x_PM_INVX1\%VDD! ( N_VDD!_MM1_s N_VDD!_c_23_n VDD! N_VDD!_MM1_b N_VDD!_c_31_p ) \
  PM_INVX1\%VDD!
x_PM_INVX1\%GND! ( N_GND!_MM0_s N_GND!_c_34_n GND! N_GND!_MM0_b N_GND!_c_42_n ) \
  PM_INVX1\%GND!
cc_1 ( N_A_MM0_g N_Z_MM0_d ) capacitor c=0.0134654f
cc_2 ( A N_Z_MM0_d ) capacitor c=0.0128328f
cc_3 ( N_A_MM1_g N_VDD!_MM1_s ) capacitor c=0.00495734f
cc_4 ( A N_VDD!_MM1_s ) capacitor c=0.00457153f
cc_5 ( N_A_c_5_p N_VDD!_MM1_s ) capacitor c=2.12927e-19
cc_6 ( N_A_MM1_g N_VDD!_c_23_n ) capacitor c=6.83531e-19
cc_7 ( N_A_MM1_g N_VDD!_MM1_b ) capacitor c=0.00138401f
cc_8 ( N_A_MM0_g N_GND!_MM0_s ) capacitor c=0.00284806f
cc_9 ( A N_GND!_MM0_s ) capacitor c=0.00348315f
cc_10 ( N_A_MM0_g N_GND!_c_34_n ) capacitor c=6.08173e-19
cc_11 ( N_A_MM0_g N_GND!_MM0_b ) capacitor c=3.76006e-19
cc_12 ( N_Z_MM0_d N_VDD!_MM1_s ) capacitor c=0.00899139f
cc_13 ( N_Z_MM0_d N_VDD!_c_23_n ) capacitor c=0.00422637f
cc_14 ( N_Z_MM0_d N_VDD!_MM1_b ) capacitor c=0.00644008f
cc_15 ( N_Z_MM0_d N_GND!_MM0_s ) capacitor c=0.00899139f
cc_16 ( N_Z_MM0_d N_GND!_c_34_n ) capacitor c=0.0106885f
cc_17 ( N_Z_MM0_d N_GND!_MM0_b ) capacitor c=0.0085131f
cc_18 ( N_VDD!_MM1_s N_GND!_MM0_s ) capacitor c=7.55743e-19
cc_19 ( N_VDD!_c_23_n N_GND!_c_34_n ) capacitor c=0.00124773f
cc_20 ( N_VDD!_MM1_b N_GND!_MM0_b ) capacitor c=0.00144067f
cc_21 ( N_VDD!_c_31_p N_GND!_c_42_n ) capacitor c=9.1113e-19


If the above simulation gets too slow, you can run without resistive parasitics but with less accuracy. To do this, change the extraction type to "C+CC" instead of "R+C+CC".

Now, you are ready to run a back-annotated simulation.

Back-Annotated Simulation

To run simulations, copy the .pex, .pxi and .netlist file to your prior Hspice simulation directory.

Rename the .netlist file to just "netlist". This will over-write your original netlist without parasitics. Now we need to do one hack to get this to work. In the netlist file, comment out the subckt and ends lines so the file looks something like this: 

// File: invx1.pex.netlist
// Created: Thu Oct  1 15:02:59 2009
// Program "Calibre xRC"
// Version "v2008.3_16.12"
// 

include "invx1.pex.netlist.pex"
//subckt invx1 (  )
// 
// GND!	GND!
// VDD!	VDD!
// Z	Z
// A	A
MM0 ( N_Z_MM0_d N_A_MM0_g N_GND!_MM0_s N_GND!_MM0_b ) NMOS_VTL l=5e-08 w=9e-08 \
 ad=9.45e-15 as=9.45e-15 pd=3.9e-07 ps=3.9e-07
MM1 ( N_Z_MM1_d N_A_MM1_g N_VDD!_MM1_s N_VDD!_MM1_b ) PMOS_VTL l=5e-08 \
 w=1.8e-07 ad=1.89e-14 as=1.89e-14 pd=5.7e-07 ps=5.7e-07
// 
include "invx1.pex.netlist.INVX1.pxi"
// 
//ends INVX1
// 
//


Now, re-run Hspice as before. Make sure the "netlist" option is checked so that it generates new input for Hspice from your new netlist:


Everything else should be the same as before back-annotation! Now when you run your simulation and go to the waveform tool, you will see many extra nets due to the parasitic R's and C's like this:

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