Difference between revisions of "VLSI Reading Group"
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== Old Schedules == | == Old Schedules == | ||
Revision as of 17:58, 25 September 2008
Contents
Overview
The reading group will meet in E2-209 on Tuesdays 3-4pm. Students will be selected to present an informal discussion of a chosen paper. Credit (pass/fail only) for the seminar is given based on your participation.
Participants
- Matthew Guthaus
- Rigo Dicochea
- Sheldon Logan
- Jeren Semendari
- Keven Woo
- Derek C
- Seokjoong Kim
- Xuchu Hu
Fall 2008
| Date | Presenter | Paper |
|---|---|---|
| 9/30/08 | ||
| 10/7/08 | ||
| 10/14/08 | ||
| 10/21/08 | ||
| 10/28/08 | ||
| 11/04/08 | ||
| 11/11/08 | Veteran's Day (No Class) | |
| 11/18/08 | ||
| 11/25/08 | ||
| 12/02/08 |
Potential Papers
- Focus primarily on DAC 2008
- A. B. Kahng, P. Sharma, and A. Zelikovsky, "Fill for Shallow Trench Isolation CMP", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668.
- S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.
- Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. Large-scale circuit placement. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.
- S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, Perturb and Simplify: Multi-level Boolean Network Optimizer, IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.
Old Schedules
Spring 2008
| Date | Presenter | Paper | |
|---|---|---|---|
| 4/7/08 | Rigo | S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning Through Better Local Search" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333. | |
| 4/7/08 | Sheldon | Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD, 2003, pp 689-697 | |
| 4/14/08 | No class (@ ISPD) | ||
| 4/21/08 | Matt | Satisfiability (No Paper) | |
| 4/28/08 | Derek | Verilog-A & Current Work | |
| 5/5/08 | - | Out of Town | |
| 5/12/08 | Jeff | B. Mohammad, M. Saint-Laurent, P. Bassett, and J. Abraham. Cache Design for Low Power and High Yield. ISQED, 2008, pp 103-107. | |
| 5/19/08 | Keven | J. Sheaeffer D. Luebke K. Skadron A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors. ACM, 2007 | |
| 5/26/08 | Nobody | No class (Memorial Day) | |
| 6/2/08 | - | No Class | |
| 6/9/08 | - | No Class (@ DAC) |
Winter 2008
| Date | Presenter | Paper |
|---|---|---|
| 1/10/08 | - | NOT MEETING |
| 1/17/08 | Matt | M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS. |
| 1/24/08 | - | NOT MEETING |
| 1/31/08 | Yaron | Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46. |
| 1/31/08 | Rigo | F. Wang, X. Wu and Y. Xie, Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning, ASPDAC 2008. |
| 2/07/08 | - | NOT MEETING |
| 2/14/08 | Sheldon | Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003. |
| 2/14/08 | Keven | K.-C. Wu and D. Marculescu, Soft Error Rate Reduction Using Redundancy Addition and Removal , ASPDAC 2008. |
| 2/21/08 | Jeff | Liang, X., Turgay, K., and Brooks, D. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD, 2007, pp 824-830. |
| 2/21/08 | Jeff | Cacti |
| 2/28/08 | Mohammed | Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006. |
| 2/28/08 | Linh | Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD 2007, pp 450-457. |
| 3/6/08 | NO MEETING | |
| 3/13/08 | Janak H. Patel (UIUC) | CMOS Process Variations: A "Critical Operation Point" hypothesis |
