Difference between revisions of "Back Annotation"

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This needs to be updated for Spectre....
 
  
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The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. It only included the gate, source, and drain parameters that were available in the spice models. In order to include the extra interconnect parasitics, we must re-extract our FO4 inv_test layout, but with an additional flag enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view. Run LVS as you did before. After it completes, select "Build Analog" in the LVS menu. This will create a new view called "analog_extracted" that has your schematic with the back-annotated parasitics.
 
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Now, in order to get Ultrasim to actually use the the analog_extracted view, we need to do a trick. In the main library manager window, select File->New->Cell View... This will open a new window. In the new window select the cell test_setup from your library. For the tool, specify "Hierarchy-Editor". This should automatically change the view name to "config." This view allows us to specify which view provides the netlist for our simulator. Press "OK;.
 
  
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Two new windows now open. One is the "New Configuration" window and the other is the "Cadence hierarchy editor" window. In the "New Configuration" window, specify your test_setup schematic as the top cell. Then click the "Use Template..." button. In another new window, select "spectre" as the template name. This should fill in some of the global bindings as shown here:
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The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. It only included the gate, source, and drain parameters that were available in the spice models. In order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.
  
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[[Image:new_configuration.jpg|400px]]
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In order to simulate with the new extracted view, open it like you would a layout. It will open up but look ugly. Load the simulation environment just like you would in the [[Simulation Tutorial]].
  
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Run the netlist/simulate once and then view the netlist. Open the "netlist" file. You should see a bunch of transistors and capacitors but with some randomized names. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter:
  
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Click "OK" in the "New Configuration" window.
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// Library name: mylib
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// Cell name: invx1
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// View name: extracted
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\+1 (Z A _net0 _net0) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 \
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        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
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\+5 (A _net1) capacitor c=2.27853e-17 m=1
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\+4 (Z _net1) capacitor c=2.87838e-17 m=1
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\+3 (_net0 _net1) capacitor c=1.29997e-16 m=1
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\+2 (_net0 Z) capacitor c=2.87838e-17 m=1
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\+0 (Z A _net1 _net1) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 \
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        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
  
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Now, in the hierarchy editor, select the test_setup in the "Cell Bindings" area. Then, select View->Instance Table from the top menus. This should open a new section in the hierarchy editor. In order to change the view used to the analog_extracted view, find the "inv_test" cell in the instance bindings. It should say "schematic" under the view found. Most of the other symbols will say "**NONE**". That is ok since they are library elements. Now, in the "View to Use" column for the inv_test cell, click and type in "analog_extracted" as shown here:
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Find out what vdd! and gnd! are called in layout by looking at the body terminals of a PMOS and NMOS. They should all be hooked together or else your layout is not complete. In my case, it was _net0 for vdd and _net1 for gnd. Then, hook these up to vdd or gnd as shown here along with your normal stimulus:
  
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[[Image:hierarchy_editor.jpg|400px]]
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// Spectre Source Statements
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v0a (vdd _net0) resistor r=0
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v1a (gnd _net1) resistor r=0
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v0 (vdd vdd!) resistor r=0
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v1 (gnd gnd!) resistor r=0
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vdd (vdd 0) vsource dc=1.8
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gnd (gnd 0) vsource dc=0
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vin (A 0) vsource type=pulse val0=0 val1=1 period=100n delay=10n rise=0.1n fall=0.1n width=50n
  
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Make sure you click on the update icon. It looks like the complier button for Visual Studio C++
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Re-run your simulation and you should see the same behavior as the schematic-only simulation, but with different delays. If not, there is an error in your setup (assuming that LVS passed)!
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Press the tab key to move out of the field you are editing. Then select File->Save to save the new config cell view. Quit the hierarchy editor.
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In order to simulate with the new extracted view, go back to the Tools->Analog Environment from the test_setup schematic view. When the window first pops up, select Setup->Design and chose the "config" view name of test_setup. As you did before with the schematic, set up the models, analyses, and outputs to be viewed. However, now, it will be using the extracted cell view instead of the schematic cell view. To confirm that we are actually simulating extracted parasitics, you can view the netlist under Simulation->Netlist->Display in the Analog Design Environment. In the netlist, you should see:
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// Library name: MyLib
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// Cell name: inv_test
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// View name: analog_extracted
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You will also see some capcitive parasitic elements like this:
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\+74 (_net1 _15) capacitor c=3.5356e-17 m=1
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Revision as of 23:38, 13 October 2008


The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. It only included the gate, source, and drain parameters that were available in the spice models. In order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.

In order to simulate with the new extracted view, open it like you would a layout. It will open up but look ugly. Load the simulation environment just like you would in the Simulation Tutorial.

Run the netlist/simulate once and then view the netlist. Open the "netlist" file. You should see a bunch of transistors and capacitors but with some randomized names. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter: 

// Library name: mylib
// Cell name: invx1
// View name: extracted
\+1 (Z A _net0 _net0) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 \
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
\+5 (A _net1) capacitor c=2.27853e-17 m=1
\+4 (Z _net1) capacitor c=2.87838e-17 m=1
\+3 (_net0 _net1) capacitor c=1.29997e-16 m=1
\+2 (_net0 Z) capacitor c=2.87838e-17 m=1
\+0 (Z A _net1 _net1) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 \
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat

Find out what vdd! and gnd! are called in layout by looking at the body terminals of a PMOS and NMOS. They should all be hooked together or else your layout is not complete. In my case, it was _net0 for vdd and _net1 for gnd. Then, hook these up to vdd or gnd as shown here along with your normal stimulus: 

// Spectre Source Statements
v0a (vdd _net0) resistor r=0
v1a (gnd _net1) resistor r=0
v0 (vdd vdd!) resistor r=0
v1 (gnd gnd!) resistor r=0
vdd (vdd 0) vsource dc=1.8
gnd (gnd 0) vsource dc=0
vin (A 0) vsource type=pulse val0=0 val1=1 period=100n delay=10n rise=0.1n fall=0.1n width=50n

Re-run your simulation and you should see the same behavior as the schematic-only simulation, but with different delays. If not, there is an error in your setup (assuming that LVS passed)!

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