Difference between revisions of "Back Annotation"

Revision as of 15:04, 24 October 2008

The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. Spectre (or hSpice) will by default use the gate area (L and W) to estimate the gate capacitance. If there are perimeters (ps, pd) and areas (as, ad) of the source and drain like this:

m0 (Z A vdd vdd) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 \
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat

it will include those capacitances. However, it does not include any extra routing, contacts, diffusion, etc. In order to include these, you need to perform extraction and back-annotation. The extraction is similar to the device extraction you used to extract a netlist for LVS, but now it extracts parasitic devices too.

Easier Method

NOTE STILL DEBUGGING THIS METHOD

In order to include the extra interconnect parasitics, we must have done DRC, Extract, and LVS. There can be absolutely no errors in LVS. For example, even this doesn't allow backannotation:

termbad.out:
? Terminal A's type in the schematic: input, in the layout: inputOutput

You should see this at the bottom of your LVS report:

Probe files from /mada/users/mrg/LayoutTest/LVS/schematic

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:


Probe files from /mada/users/mrg/LayoutTest/LVS/layout

devbad.out:

netbad.out:

mergenet.out:

termbad.out:

prunenet.out:

prunedev.out:

audit.out:

Now, you are ready to back-annotate. In the LVS window, press the button "Build Analog". This will create a new cell view called "analog_extracted". You can view this, but it will look like a layout with some names pasted all over. This matched the parasitics from your layout with your schematic.

Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Spectre simulation as normal. (In fact, you can just load the saved setup from the spectre.run1 directory.) Confirm that it works for the schematic. Then, instead of the view being "schematic", you make it "analog_extracted" and run it again. Now it should have parasitics too!

To confirm this, look in your run directory (e.g. spectre.run1) and view the "netlist" file in the unix shell. This should have capacitances in it. If not, there is something wrong.

Old Method

In order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.

In order to simulate with the new extracted view, open it like you would a layout. It will open up but look ugly. Load the simulation environment just like you would in the Simulation Tutorial.

Run the netlist/simulate once and then view the netlist. Open the "netlist" file. You should see a bunch of transistors and capacitors but with some randomized names. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter:

// Library name: mylib
// Cell name: invx1
// View name: extracted
\+1 (Z A _net0 _net0) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 \
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat
\+5 (A _net1) capacitor c=2.27853e-17 m=1
\+4 (Z _net1) capacitor c=2.87838e-17 m=1
\+3 (_net0 _net1) capacitor c=1.29997e-16 m=1
\+2 (_net0 Z) capacitor c=2.87838e-17 m=1
\+0 (Z A _net1 _net1) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 \
        ad=1.539e-13 ps=1.35e-06 pd=1.35e-06 m=1 region=sat

Find out what vdd! and gnd! are called in layout by looking at the body terminals of a PMOS and NMOS. They should all be hooked together or else your layout is not complete. In my case, it was _net0 for vdd and _net1 for gnd. Then, hook these up to vdd or gnd as shown here along with your normal stimulus:

// Spectre Source Statements
v0a (vdd _net0) resistor r=0
v1a (gnd _net1) resistor r=0
v0 (vdd vdd!) resistor r=0
v1 (gnd gnd!) resistor r=0
vdd (vdd 0) vsource dc=1.8
gnd (gnd 0) vsource dc=0
vin (A 0) vsource type=pulse val0=0 val1=1 period=100n delay=10n rise=0.1n fall=0.1n width=50n

Re-run your simulation and you should see the same behavior as the schematic-only simulation, but with different delays. If not, there is an error in your setup (assuming that LVS passed)!