Difference between revisions of "280G W09"
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− | | | + | |Yesin Ryu, Taewhan Kim (Seoul National University),[http://bacon.cse.ucsc.edu/papers/ICCAD_08/PDFs/Papers/06A.1.pdf Clock Buffer Polarity Assignment Combined with Clock Tree Generation for Power/Ground Noise Minimization],ICCAD_08 |
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Revision as of 08:52, 15 January 2009
- Focus primarily on ICCAD 2008 (also available on bacon in /home/www/papers/ICCAD_08).
Winter 2009
Date | Presenter | Paper | |
---|---|---|---|
1/9/09 | Meeting | ||
1/16/09 | Keven | Yu Hu,Shih V,Majumdar R, Lei He (University of California Los Angeles), FPGA area reduction by multi-output function based sequential resyntheis, DAC2008. | |
1/16/09 | Seokjoong | F. Li, D. Chen, L. He, and J. Cong (University of California Los Angeles), Architecture evaluation for power-efficient FPGAs,FPGA '03 | |
1/23/09 | Xuchu | Yesin Ryu, Taewhan Kim (Seoul National University),Clock Buffer Polarity Assignment Combined with Clock Tree Generation for Power/Ground Noise Minimization,ICCAD_08 | |
1/23/09 | |||
1/30/09 | |||
1/30/09 | |||
2/6/09 | |||
2/6/09 | |||
2/13/09 | |||
2/13/09 | |||
2/20/09 | |||
2/20/09 | |||
2/27/09 | |||
2/27/09 | |||
3/6/09 | |||
3/6/09 | |||
3/13/09 | |||
3/13/09 |