Difference between revisions of "280G W09"
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| Overview of UCI's: NISC (No Instruction Set Computer) Technology (resembles High-Level Synthesis) http://www.ics.uci.edu/~nisc | | Overview of UCI's: NISC (No Instruction Set Computer) Technology (resembles High-Level Synthesis) http://www.ics.uci.edu/~nisc | ||
Please get these articles from: http://www.ics.uci.edu/~nisc/publications/publications.html (& look over site) | Please get these articles from: http://www.ics.uci.edu/~nisc/publications/publications.html (& look over site) | ||
− | Papers: #11. "Designing a Custom Architecture for DCT Using NISC Technology" ( | + | Papers: #11. "[http://cecs02.cecs.uci.edu/utils/Download.aspx?f=gorjiara-aspdac06-nisc.pdf&to= Designing a Custom Architecture for DCT Using NISC Technology]" (2 page summary) |
− | Technical Reports, #2: TR05-11: "NISC Technology and Preliminary Results" | + | Technical Reports, #2: TR05-11: "[http://cecs02.cecs.uci.edu/utils/Download.aspx?f=TR05-11.pdf&to= NISC Technology and Preliminary Results]" |
|- | |- | ||
| 1/30/09 | | 1/30/09 |
Revision as of 01:18, 27 January 2009
- Focus primarily on ICCAD 2008 (also available on bacon in /home/www/papers/ICCAD_08).
Winter 2009
Date | Presenter | Paper | |
---|---|---|---|
1/9/09 | Meeting | ||
1/16/09 | Keven | Yu Hu,Shih V,Majumdar R, Lei He (University of California Los Angeles), FPGA area reduction by multi-output function based sequential resyntheis, DAC2008. | |
1/16/09 | Seokjoong | F. Li, D. Chen, L. He, and J. Cong (University of California Los Angeles), Architecture evaluation for power-efficient FPGAs,FPGA '03 | |
1/23/09 | Xuchu | Yesin Ryu, Taewhan Kim (Seoul National University),Clock Buffer Polarity Assignment Combined with Clock Tree Generation for Power/Ground Noise Minimization,ICCAD_08 | |
1/23/09 | Sheldon | Yong Zhan, Yan Feng, Sachin S. Sapatnekar(University of Minnesota),A Fixed Die Floorplanning Algorithm using an Analytical Approach, ASPDAC 06 | |
1/30/09 | Marcelo | Overview of UCI's: NISC (No Instruction Set Computer) Technology (resembles High-Level Synthesis) http://www.ics.uci.edu/~nisc
Please get these articles from: http://www.ics.uci.edu/~nisc/publications/publications.html (& look over site) Papers: #11. "Designing a Custom Architecture for DCT Using NISC Technology" (2 page summary) Technical Reports, #2: TR05-11: "NISC Technology and Preliminary Results" | |
1/30/09 | Jeff | Sharifkhani, M.; Sachdev, M.(IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 2, FEBRUARY 2007),Segmented Virtual Ground Architecture for Low-Power Embedded SRAM, IEEE 2007 | |
2/6/09 | |||
2/6/09 | |||
2/13/09 | |||
2/13/09 | |||
2/20/09 | |||
2/20/09 | |||
2/27/09 | |||
2/27/09 | |||
3/6/09 | |||
3/6/09 | |||
3/13/09 | |||
3/13/09 |