Cadence Encounter

Overview

To use the Cadence tools, you must change this environment variable:

export OSUcells=/mada/software/techfiles/osu_soc_v2.7/cadence 

The OSU scripts for Cadence can be copied from here:

cp -rf /mada/software/techfiles/osu_soc_v2.7/cadence/flow/ami035

but they are for an old version of Encounter. Quite a few things have changed, so I am posting a description of the working script I made by modifying the old OSU scripts.

You will need to specify the correct top-level name and gate-level netlist name in encounter.conf. This keeps variables and constants used in the placement and routing scripts.

Running Scripts

To run encounter, you simply can run:

 encounter

at the Linux shell prompt.

In this tutorial, I may not explicitly mention the GUI menu commands, because it is more convenient to use the shell interface. However, most of these commands are available (with forms for options) under the appropriate menus (e.g. Timing, Place, Floorplan, etc.). I suggest that you use the GUI for the first time along with the "-cmd foo.log" argument to save your actions/commands to a file called foo.log. You can then create a script from the saved file.

To run a script, type:

encounter -init encounter.tcl

with X11 exported to your local machine. If this completes successfully, you can hit "f" to center the layout.

In the terminal window where you ran encounter, you should see the shell prompt:

 encounter 1>

This is where you enter commands if you do not use the GUI.

Typical Design Flow

A typical design flow involves subsequently refined layout steps. The first step is a course planning of the chip called floorplanning. This is followed by IO and cell placement, special net routing, clock tree synthesis, in-place optimization, and finally global and detailed routing.

Between most of these steps we perform a timing analysis on the circuit to determine its performance and see if we need to back up. The timing analysis is run with the following commands:

 buildTimingGraph
 timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS

The options to the command timeDesign will change depending on which part of the flow you are in.

Your design is read in by modifying the .conf file in the flow. There are specific lines to specify: the IO pads (.io), the input netlist (.mapped.v), the Synopsys design constraint file (.sdc), the timing library format (.tlf) file, the layout exchange format (.lef) file (which is the actual cell pins and boundaries), and numerous other parameters. This is loaded with the following command:

 loadConfig ./encounter.conf 
 commitConfig

Floorplanning

The floorplan stage defines the rows that the standard cells will go in. For small designs, it is sufficient to make a single floorplan and place everything in the hierarchy at once. This is called "flat" placement. If you have a large design or memories, you may have to customize this floorplan a little more by specifying the relative locations and sizes of the different blocks (sub-modules of your entire design) and the locations of the fixed size memories.

You can create a flat floorplan like this:

 floorplan -r 1.0 0.9 1 1 1 1

This says that it should have a 1.0 aspect ratio (height to width), 90% row utilization, and have space of size "1" around the core. (This is probably in the default units specified in the .lef file.)

After you specify the rows, you also need to specify how the vdd and gnd signals connect to the rows. This is done by adding a power ring around the perimter of the design and stripes internal to the design. To really know the size of these wires, you will have to do power grid analysis after placement. This is not required in this project.

 addRing -spacing_bottom 10 -width_left 10 -width_bottom 10 -width_top 10 -spacing_top 10 -layer_bottom metal3 -width_right 10 -around core -center 1 -layer_top metal3 -spacing_right 10 -spacing_left 10 -layer_right metal4 -layer_left metal4 -nets { gnd vdd }
 addStripe  -set_to_set_distance 100 -spacing 5 -xleft_offset 50 -layer metal4 -width 5 -nets { gnd vdd }

Placement

After the power is specified, you can place the cells in your design using the following command:

 amoebaPlace

Special Net Routing

Once the cells are placed, you can connect the power stripes and rings to the standard cell rows.

 sroute -noBlockPins -noPadRings

You should also perform a trial routing to see if any cell pins are inaccessible due to power routing:

 trialroute

At this time, it is a good idea to do Pre-CTS Timing Analysis:

 buildTimingGraph
 timeDesign -preCTS -idealClock -numPaths 10 -prefix preCTS

This will give you an idea if your placement is way off and there is no chance for timing. If this is the case, you will likely have to change your IO assignment or change your floorplan.

Clock Tree Synthesis

 createClockTreeSpec -output encounter.cts
 addCTSCellList CLKBUF1 CLKBUF2 CLKBUF3
 clockDesign -clk clk

 extractRC
 reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt

 setAnalysisMode -checkType setup -asyncChecks async -skew true -clockPropagation sdcControl
 buildTimingGraph
 timeDesign -postCTS -numPaths 10 -prefix postCTS

Post-CTS In-Place Optimization

 setExtractRCMode -engine preroute -assumeMetFill
 extractRC
 optDesign -postCTS

 buildTimingGraph
 timeDesign -postCTS

Filler Cells

 addFiller -cell FILL -prefix FILL -fillBoundary

Routing

 globalNetConnect vdd -type tiehi
 globalNetConnect vdd -type pgpin -pin vdd -override
 globalNetConnect gnd -type tielo
 globalNetConnect gnd -type pgpin -pin gnd -override
 globalDetailRoute

 setExtractRCMode -engine postRoute 
 extractRC
 optDesign -postRoute

 setExtractRCMode -engine postRoute
 extractRC
 buildTimingGraph
 #timeDesign -signOff # need to install qrc to use this
 timeDesign -postRoute

Final Check

 verifyGeometry
 verifyConnectivity -type all

Save Output

 streamOut final.gds2 -mapFile gds2_encounter.map -stripes 1 -units 1000 -mode ALL
 saveNetlist -excludeLeafCell final.v

 rcout -spf final.dspf

Overview of File Types

.lib/.db

.lef

.tcl/.scr

.v/.mapped.v

.io

Notes on 45nm

If you want to synthesize a design using the Nangate FreePDK45 cell library, you need to make a few changes:

1) You need to compile the Nangate .lib into a .db and use that. To do this, run:

dc_shell-t

Then execute these commands:

read_lib /mada/software/techfiles/NangateOpenCellLibrary_PDKv1_3_v2009_07/liberty/NangateOpenCellLibrary_typical_conditional_ccs.lib  
write_lib NangateOpenCellLibrary

which will create a file NangateOpenCellLibrary.db. Move that to your project directory.

2) Then, these lines change to the compile_dc.tcl:

set search_path [concat  $search_path . ]
set link_library [set target_library [concat  [list NangateOpenCellLibrary.db ] [list dw_foundation.sldb]]]

3) In the encounter.conf, you need to reference the .lib file instead of the .tlf file. You also need to point to the .lef file. Specifically, these lines change:

set OSUcells /mada/software/techfiles/NangateOpenCellLibrary_PDKv1_3_v2009_07
set rda_Input(ui_timelib) "$OSUcells/liberty/NangateOpenCellLibrary_typical_conditional_ccs.lib"
set rda_Input(ui_leffile) "$OSUcells/lef/NangateOpenCellLibrary.lef"