Back Annotation

The above simulation did not actually include the parasitic capacitances and resistances of the interconnect. Spectre (or hSpice) will by default use the gate area (L and W) to estimate the gate capacitance, but additional poly is not considered. If you specified perimeters (ps, pd) and areas (as, ad) in the pcell form, it will include those estimates in simulation. However, it does not include any extra routing, contacts, diffusion, etc. In order to include these, you need to perform parasitic extraction and back-annotation. The extraction is similar to the device extraction you used to extract a netlist for LVS, but now it extracts parasitic resistances and capacitances too.

Your design must pass DRC and LVS to do this.

Extract Parasitics

This is very similar to LVS. Go to Calibre->Run PEX. You will need to specify a layer map like LVS again. Also, select the rule file as this:

/mada/software/techfiles/FreePDK45/ncsu_basekit/techfile/calibrexRC.rul

Under the Input section, in the Layout tab, make sure that GDSII and "Export from layout viewer" are selected. Under the Netlist tab, make sure that SPICE and "Export from schematic viewer" are selected.

Under the Output section, most options should be left as default. By default, "All Nets" under the Nets tab should be checked. Under the Report tab, select "Generate PEX report" and "View report after PEX finishes". Under SVDB, make sure that "Start RVE after

Now, you are ready to back-annotate. However, in order to include the extra interconnect parasitics, we must re-extract our layout, but with an additional flags enabled. When you select Verify->Extract in the layout window, click the "Set Switches" button. This will open an additional window with a set of options. Highlight the "Extract_parasitic_caps" option. This will put parasitic resistors and capacitors in the new extracted view.

After re-running LVS, in the LVS window, press the button "Build Analog". If there was an LVS problem, it will just say "There was an LVS error." If there wasn't, this will open a second window. Just press ok to "Include All". This will create a new cell view called "analog_extracted". You can open this new view and it will look like a mash-up of your schematic and layout. This matched the parasitics from your layout with your schematic. It is pretty hard to see details in a big layout though.

Then, to simulate the back-annotated view, you simply go to your Schematic and set up your Spectre simulation as normal. (In fact, you can just load the saved setup from the spectre.run1 directory.) Confirm that it works for the schematic. Then, go to Spectre->Netlist and Simulate, but instead of the view being "schematic", you make it "analog_extracted" and run it again like this:

Now it should have parasitics too!

To confirm this, look in your run directory (e.g. spectre.run1) after you run a back-annotated simulation and view the "netlist" file in the unix shell (or go to Spectre->Stimulus->Edit Netlist File) and you should see a bunch of transistors and capacitors. The inputs should be named normally, but other internal nets may not. Here is an example from my inverter:

// Library name: mylib
// Cell name: invx1
// View name: analog_extracted
\+1 (Z A vdd! vdd!) tsmc18dP w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat
\+5 (A 0) capacitor c=2.27853e-17 m=1
\+4 (Z 0) capacitor c=2.87838e-17 m=1
\+3 (vdd! 0) capacitor c=1.29997e-16 m=1
\+2 (vdd! Z) capacitor c=2.87838e-17 m=1
\+0 (Z A 0 0) tsmc18dN w=2.7e-07 l=1.8e-07 as=1.539e-13 ad=1.539e-13 \
        ps=1.35e-06 pd=1.35e-06 m=1 region=sat

If you do not see the capacitors, then something is wrong.