280G F12
This quarter, we will put a focus on resonant and non-traditional clocking. We will have two presenters each day -- about 30-40 min each. Please select papers on either distributed/monolithic LC, rotary clocking, or standing wave clocking or similar non-traditional clocking papers.
Date | Presenter | Topic/Paper |
---|---|---|
10/03/12 | Raj,Blake,Seokjoong | VLSI-SOC Dry Run ** Will need to start at 10:30am sharp |
10/10/12 | NONE (VLSI-SoC) | |
10/17/12 | NONE (Matt at NSF) | |
10/24/12 | Matt | How to review papers, Read the clock survey I wrote |
10/31/12 | Raj | Standing Wave Clocking |
11/07/12 | NONE (Matt at ICCAD) | |
11/14/12 | Riadul | |
11/21/12 | Ben | |
11/28/12 | Bin | |
12/05/12 | Hany |
Date | Presenter | Topic/Paper |
---|---|---|
/13 | Rafael | |
/13 | Elnaz | |
/13 | Jeff | |
/13 | Nihan | |
/13 | ||
/13 |
Resonant Papers:
Uniform-phase uniform-amplitude resonant-load global clock distributions
Resonant clocking using distributed parasitic capacitance,
Jitter Characteristic in Charge Recovery Resonant Clock Distribution,
Design of resonant global clock distributions
Resonant-Clock Latch-Based Design
Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor
A. Ishii, et al., “A Resonant Clock 200MHz ARM926EJ-STM Microcontroller,” European Solid-State Circuits Conf., pp. 356-359, 2009.
WOOD, J., EDWARDS, T. C., AND LIPA, S. 2001. Rotary traveling-wave oscillator arrays: A new clock tech- nology. Journal of Solid-State Circuits (JSSC) 36, 11, 1654–1664.
TASKIN, B., DEMAIO, J., FARELL, O., HAZELTINE, M., AND KETNER, R. 2009. [http://dl.acm.org/citation.cfm?id=1529266 Custom topology rotary clock router with tree subnetworks]. Transactions on Design Automation of Electronic Systems (TODAES) 14, 3.
These two would go together:
GUTHAUS, M. R. 2011. Distributed LC resonant clock tree synthesis. In International Symposium on Circuits
and Systems (ISCAS). 1215–1218. && CONDLEY, W., HU, X., AND GUTHAUS, M. 2011. A methodology for local resonant clock synthesis using lc-assisted local clock buffers. In International Conference on Computer-Aided Design (ICCAD). 503–506.
HU, X. AND GUTHAUS, M. 2012. Distributed LC resonant clock grid synthesis. IEEE Transactions on Circuits and Systems I (TCAS-I).
HU, X., CONDLEY, W., AND GUTHAUS, M. 2012. Library-aware resonant clock synthesis. In Design Automa- tion Conference (DAC).
ROSENFELD, J. AND FRIEDMAN, E. 2006. Design methodology for global resonant h-tree clock distribution networks. International Symposium on Circuits and Systems (ISCAS). **there is a journal version of this too**
CHAN, S., RESTLE, P., SHEPARD, K., JAMES, N., AND FRANCH, R. 2004. A 4.6GHz resonant global clock distribution network. International Solid-State Circuits Conference (ISSCC), 342 – 343.
CHAN, S. C., SHEPARD, K. L., AND RESTLE, P. J. 2003. Design of resonant global clock distributions. International Conference on Computer Design (ICCD).
YU, Z. AND LIU, X. 2009. Implementing multiphase resonant clocking on a finite-impulse response filter. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, 11, 1593 – 1601.
The following are not resonant papers:
Variability:
Efficient coupled noise estimation for on-chip interconnects
Practical clock tree robustness signoff metrics
Process variation aware clock tree routing
SSTA:
Statistical timing analysis considering spatial correlations using a single PERT-like traversal
Statistical timing analysis using bounds and selective enumeration
First-order incremental block-based statistical timing analysis
Statistical timing analysis: From basic principles to state of the art
Statistical static timing analysis: A survey
Statistical clock skew analysis considering intra-die process variations
Statistical analysis of clock skew variation in H-tree structure
Implementation:
The clock distribution of the POWER4 microprocessor
A 5GHz duty-cycle correcting clock distribution network for the POWER6 microprocessor
Multi-GHz clocking scheme for Intel Pentium 4 microprocessor
Myth busters: Microprocessor clocking is from mars, asic’s clocking is from venus?
Clocking design and analysis for a 600-MHz Alpha microprocessor
A 300-MHz 64-b quad-issue CMOS RISC microprocessor
A 200-MHz 64-b dual-issue CMOS microprocessor
The design and analysis of the clock distribution network for a 1.2GHz alpha microprocessor
Other:
Clock distribution networks in synchronous digital integrated circuits
Post-processing of clock trees via wiresizing and buffering for robust design
Practical techniques to reduce skew and its variations in buffered clock networks