ATC

Automatic Testbench Creator (ATC)

The ATC is a VPI testbench creator, it processes a verilog topfile, which is the device under test (DUT).
By processing the DUT, the ATC creates an object with inputs and outputs which are exactly the same as the DUT.

• aunit.v *

module alu_add(input int data1, input int data2, output int out);

 always_comb begin
     out = data1 + data2;
  end

end module

The ATC created testbench will give access to data1, data2 and out, which is the complete interface of aunit.v

1. Implementation:

The ATC is integrated into rake. To use it, edit the xml file in your top directory of the module.

• In the testbench xml tag, add the ttb attribute, and set it to the name of your DUT.
  This assumes that the dut.v file is relative to rtl/dut.v, and the output of the ATC will be to tests/

1. ce.xml # (Excerpt taken)

... <testbench base="salu_tb" suite="vcs" ttb="salu.v">

   <verilog>
     tests/salu_tb.v
   </verilog>
   <source>
     tests/salu_tb.cpp
   </source>
   <tab>tests/salu_tb.tab</tab>
 </testbench>

...