ATC

Automatic Testbench Creator (ATC)

The ATC is a VPI testbench creator, it processes a verilog topfile, which is the device under test (DUT).
By processing the DUT, the ATC creates an object with inputs and outputs which are exactly the same as the DUT.

aunit.v

module alu_add(input int data1,
 input int data2,
 output int out);
   always_comb begin
      out = data1 + data2;
   end
end module

The ATC created testbench will give access to data1, data2 and out, which is the complete interface of aunit.v

==Implementation:==
The ATC is integrated into rake. To use it, edit the xml file in your top directory of the module.

• In the testbench xml tag, add the ttb attribute, and set it to the name of your DUT.
  This assumes that the dut.v file is relative to rtl/dut.v, and the output of the ATC will be to tests/

• ce.xml (Excerpt taken)
  

<testbench base="salu_tb" suite="vcs" ttb="salu.v">
   <verilog>
     tests/salu_tb.v
   </verilog>
   <source>
     tests/salu_tb.cpp
     tests/salu_ttb.cpp
   </source>
   <tab>tests/salu_tb.tab</tab>
 </testbench>

• This will create the complete interface for your testbench int the tests/ directory
• Note that both tb.cpp and ttb.cpp files have to be in the xml file for VCS to compile them. Order does not matter.

1. dut_tb.v - The verilog testbench, VCS will run this (Autogenerated every time your run rake)
   
2. dut_tb.cpp - Your VPI testbench, C++ (Autogenerated only if file doesn't exist)
   
3. dut_tb.h - Any vars / stuff you need for your tb (Autogenerated only if file doesn't exist)
   
4. dut_ttb.h - VPI definitions, defines object that you use to communicate to ports of DUT (Autogenerated every time your run rake)
   
5. dut_ttb.cpp - VPI Testbench backend, communication with VCS... (Autogenerated every time your run rake)
   
6. dut_ttb.tab - VCS file that correlates verilog functions with C++ VPI functions (Autogenerated every time your run rake, deprecated)
   

</p>

Running the initially created tb

[agolubev@mascd2 atcexample]$rake test:atcexample_tb
(in /mada/users/agolubev/scoore)
cd /mada/users/agolubev/scoore/projects/scoore/atcexample

Warning-[ACC_CLI_ON] ACC/CLI capabilities enabled
ACC/CLI capabilities have been enabled for the entire design. For faster
performance enable module specific capability in pli.tab file

50 modules and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
g++ -pipe -Wno-write-strings -I/mada/software/synopsys/vcs//include -I/mada/users/agolubev/scoore/projects/scoore/synthesis/rtl
-I/mada/users/agolubev/scoore/storage/rtl -I/mada/users/agolubev/scoore/memcell/rtl -I/mada/users/agolubev/scoore/projects/scoore/common/rtl
-I/mada/users/agolubev/scoore/projects/scoore/atcexample/rtl -O -I/mada/software/synopsys/vcs/include -c ../tests/atcexample_tb.cpp
g++ -pipe -Wno-write-strings -I/mada/software/synopsys/vcs//include -I/mada/users/agolubev/scoore/projects/scoore/synthesis/rtl
-I/mada/users/agolubev/scoore/storage/rtl -I/mada/users/agolubev/scoore/memcell/rtl -I/mada/users/agolubev/scoore/projects/scoore/common/rtl
-I/mada/users/agolubev/scoore/projects/scoore/atcexample/rtl -O -I/mada/software/synopsys/vcs/include -c ../tests/atcexample_ttb.cpp
../simv up to date
full clock set to 10ns

                       Testbench Seeded with 1247602844



@D atcexample_tb check(): tb_cycle[0]

@D atcexample_tb check(): tb_cycle[1]

@D atcexample_tb check(): tb_cycle[2]

@D atcexample_tb check(): tb_cycle[3]

@D atcexample_tb check(): tb_cycle[4]

@D atcexample_tb check(): tb_cycle[5]

@D atcexample_tb check(): tb_cycle[6]

@D atcexample_tb check(): tb_cycle[7]

@D atcexample_tb check(): tb_cycle[8]

@D atcexample_tb check(): tb_cycle[9]



10 Clock Cycles Total atcexample_tb FINISHED

When the tb is first run, the check() fn prints out a variable, (num_total_ops) which corresponds to the clock cycle count.

Note: clock cycle count starts at 0

The tb also has a verilog variable tb_cycle, that one may add to the wave viewer. This is to aid debugging.
In the example above, the check() fn prints out the tb_cycle variable, which is set in the set() fn.

Troubleshooting:

Q: Error-[ITSFM] Illegal `timescale for module

  /mada/users/agolubev/scoore/projects/scoore/l0d/rtl/SRAM_1W_1R_3x64test.v, 25  

    Module "SRAM_1W_1R_3x64test_v" has `timescale but previous module(s) do not.v  

    Please refer LRM 1364-2001 section 19.8.  

A: As of verilog 2001, we do not use the `timescale directive.

  This is set in the _ttb.v file, so that we can parametrize it and test for power.    

  

  The following command inline removes all `timescale directives.  Use with caution, but is tested.  

  sed -i 's/`timescale.*//' rtl/*.v

WORK IN PROGRESS