Leon3
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Contents
Tom Golubev's Leon3 Based Logic Analyzer
Using NIOSII Cyclone dev board
Leon3 grlib-gpl-1.0.20-b3403
FPGA Usage (1): EP1C20F400C7 Configuration: LUT Usage (%) Mem Usage (%) System MHz (1) Default: noFpu, noMMU 56 % 36 % 135.9 (2) noFPU, MMU 65 % 37 % 134.8 (3) Bare 38 % 18 % 126.1
(1) Command Used: make distclean && time `make synplify && make quartus-synp`
Adding ADCDAC Tutorial
1) Edit config.in to add options to xconfig
2) add to leon3XX.vhd in the designs/your_board directory library gleichmann; use gleichmann.hpi.all; use gleichmann.miscellaneous.all; use gleichmann.multiio.all; use gleichmann.dac.all; use gleichmann.sspi.all; use gleichmann.ge_clkgen.all; use gleichmann.ac97.all;
3) Add signals for ADC in structure (leon3XX.vhd) 4) Add generate section into structure (leon3XX.vhd) 5) Removed gleichman from LIBSKIP (Makefile) 6) Copied leon3hpe.h file into project dir, because config.vhd.in file imported it
Programming Board
using grmon: add to path - #export PATH=$PATH:/home/tom/leon3/grmon-eval/linux add libjtag.so from quartus 32 bit #export LD_LIBRARY_PATH=/software/altera/quartus/linux
envoke grmon, #grmon-eval -altjtag
To use grmon-rcp, libwidget_gtk2.so 32 bit needs to be present
A 32-bit Java also need to be used Install 32 bit openjdk Switch from 64 to 32 bit java #alternatives --config java #alternatives --config javac
Design Questions
1) How easy is it to have mixed VHDL / Verilog Design using Synplify?
2) How much throughput is needed?
3) Which bus to use? AHB, APB? or tightly couple to proc (difficult)
Wishbone / AHB / CoreConnect http://es.elfak.ni.ac.yu/Papers/ICEST%20'06.pdf BEE2 Leon2 ahb bus explanation http://cadlab.cs.ucla.edu/software_release/bee2leon3port/files/Timothy_Wong-MS_Report.pdf
==AMBA BUS Notes:== (From 1999 ARM ihi 0011A Document)
AMBA signal names
All AMBA signals are named such that the first letter of the name indicates which bus
the signal is associated with. A lower case n in the signal name indicates that the signal
is active LOW, otherwise signal names are always all upper case.
Test signals have a prefix T regardless of the bus type. More information on test signals
can be found in Chapter 6 AMBA Test Methodology.
Important Sources / Documents: Nios II / Leon2 Comparison CoSCPU.pdf Leon2 / MicroBlaze / OpenRISC1200 Comparison Evaluation_of_synthesizable_CPU_cores.pdf
Links
Comparison of many soft cpus - http://www.1-core.com/library/digital/soft-cpu-cores/
Evaluation of synthesizable CPU cores
NIOS2 to Leon2 - http://www.altera.com/literature/dc/2007/in_2007_multiproc.pdf
Tutorial of adding AHB Slave to Leon2 http://www.ece.ncsu.edu/muse/soc_information/tutorial/leon/
Another paper of Leon2 APB addon http://www.iberchip.org/iberchip2006/ponencias/45.pdf
Dutch university research into SOCs, includes NIOS2 Cyclone Dev board http://emsys.denayer.wenk.be/?project=empro&page=about Porting to AHB / Wishbone buses report - http://emsys.denayer.wenk.be/empro/OCIDEC%20case%20report.pdf
GRADCDAC - tmtc.pdf (13-24)
AMBA Spec IHI0011A_AMBA_SPEC.pdf
GRADCDAC RTEMS Driver rtems-gaisler-drivers-1.1.99.4.0.pdf (92-101)
Gaisler IP grip.pdf (533-558,563-570)
Sources
(ASAP 2006). S. Tillich and J. Großsch¨adl. Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. In Cryptographic Hardware and Embedded Systems — CHES 2006, vol. 4249 of Lecture Notes in Computer Science, pp. 270–284. Springer Verlag, 2006.
A. Hodjat, I. Verbauwhede : Interfacing a high speed crypto accelerator to an embedded CPU. In: Proceedings of the 38th Asilomar Conference on Signals, Systems, and Computers, vol. 1, pp. 488–492. IEEE, New York (2004) P. Schaumont, K. Sakiyama, A. Hodjat, and I. Verbauwhede.
Embedded Software Integration for Coarse-Grain Reconfigurable Systems. In Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), pp. 137–142, IEEE CS Press, 2004.
An AES Tightly Coupled Hardware Accelerator in an FPGA-based Embedded Processor Core
