Ultrasim and Spectre

For analog circuits described in Verilog - A include the following command into the file that runs Ultrasim, preferably toward the end: ahdl_include "<file>"

To instantiate the models in the netlist, you can simply refer to it via a call to its module name.

Example:

Verilog-A module:

`include "constants.vams"
`include "disciplines.vams"
module inverter(in, out);
 input in;
 output out;
 electrical in, out;
parameter real high = 1.0
parameter real low = 0.0;
parameter real margin = 0.5;
analog begin
 if (in < noise margin)
   out = high;
 else
  out = low;
end
endmodule

Netlist file in Spectre Language :

... I0 (input, output) inverter ... ahdl_include inverter.va