VLSI Reading Group

Overview

The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.

Participants

• Matthew Guthaus
• Rigo Dicochea
• Sheldon Logan
• Keven Woo
• Mohammed Jamil
• J. Semendari
• Yaron Kretchmer

Schedule

Date	Presenter	Paper
1/10/08	-	NOT MEETING
1/17/08	Matt	M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS.
1/24/08	-	NOT MEETING
1/31/08	Yaron	Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
1/31/08	Rigo	F. Wang, X. Wu and Y. Xie, Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning, ASPDAC 2008.
1/24/08	-	NOT MEETING
2/14/08	Sheldon	Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003.
2/14/08	Keven	K.-C. Wu and D. Marculescu, Soft Error Rate Reduction Using Redundancy Addition and Removal , ASPDAC 2008.
2/21/08	Jeff	Liang, X., Turgay, K., and Brooks, D. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD, 2007, pp 824-830.
2/21/08	Linh	TBD
2/28/08	Mohammed	TBD
2/28/08	TBD	TBD
3/6/08	TBD	TBD
3/6/08	TBD	TBD
3/13/08	TBD	TBD
3/13/08	TBD	TBD

Potential Papers

• A. B. Kahng, P. Sharma, and A. Zelikovsky, "Fill for Shallow Trench Isolation CMP", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668.

• S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.

• Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. Large-scale circuit placement. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.

• S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, Perturb and Simplify: Multi-level Boolean Network Optimizer, IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.

• http://www.ece.rice.edu/~kmram/publications/dft03.pdf

• Other papers from ICCAD 2007.