MASC/Elastic System

Elastic System Tutorial

This tutorial is to demonstrate how to create an Elastic System design using the default MASC synthesis flow. The first you need, if you're not yet, is to familiarize with the concept of Elastic System, the following papers should give a good introduction to the topic SELF, LI_BDN and LIDs.

There is one important difference between the approaches in these papers and the approach we use in the lab. The previous approaches have an automated flow that convert regular synchronous RTL code into elastic systems. This leads to some limitations in the types of transformations that are possible in the circuits. In the approach adopted at MASC, we require the designer to explicit write RTL using the elastic syntax. For that, we provide a custom implementation of the elastic buffer, that must be declared in the RTL code. Also, the handshake signals have to be generated by the designer.

Once you know enough about the concept of Elastic Systems, you need to get access to the RTL repo of the MASC lab (mascrtl), check instructions GIT_Repository. In the remainder of this tutorial, <mascrtl> will indicate directory to which the repository was checked-out. Thus, <mascrtl>/code indicates the directory code inside the mascrtl repository, and so forth.

Glossary

A couple of remarks that may be useful for mapping the contents of the papers into the vocabulary used here.

• Elastic Systems, Latency Insensitive and Synchronous with Handshakes: different names used in the literature, indicate the same thing (or almost the same thing).
• Valid and Stop signals are the handshakes signals used in the papers. LI-BDNs uses queue operations intead (enqueue, dequeue, empty and full. Although our papers also use valid/stop, in our verilog the names used are valid and retry.
• Elastic buffers are called stages in our verilog, but are essentially the same thing.

Methodology

The tutorial starts by presenting a simple circuit, to get the reader familiarized with the flow and the behavior and testing of elastic. We will call this circuit "Hello, Elastic". It consists of a simple buffer that returns '0' if the input is odd, and returns the input divided by two if it is even. A testbench will also be generated to verify the functionality. Then, we are going to create an elastic multiplier, with the relevant testbench. The topology used for the multiplier is the so-called shift-adder, which takes an arbitrary number of cycles to complete.

Hello Elastic

Creating an RTL project

Start by creating a new project, named 'hello' as described in Synthesis Setup. Your XML file should be (look at ATC for more information):

hello.xml

 <project name="hello">
   <requires>retry</requires>
   <asic frequency="1000" test="90" suite="dc"/>
   <asic base="hello"/>
   <catalyst base="hello" test=""/>
   <fpga base="hello" tool="synplify"/>
   <testbench base="hello_tb" suite="vcs" ttb="hello.v">
     <verilog>
       tests/hello_tb.v
     </verilog>
     <tab>
       tests/hello_tb.tab
     </tab>
     <source>
       tests/hello_tb.cpp
       tests/hello_ttb.cpp
     </source>
   </testbench>
   <regression target="test">hello_tb</regression>
   <regression target="asic">hello</regression>
   <regression target="fpga">hello</regression>
 </project>

This will be a simple module that checks the parity of the First, let's write the code for our elastic adder In <mascrtl>/code/hello/rtl/hello.v, write

        import blabla

Now, we need a testbench for the newly generated circuit. For that run:

 rake test:all v=1 grid=1

You will note a new directory named 'tests/' in you project folder.

Multiplier

(Explain arithmetically how the multiplier works).