Overview
The reading group will meet in E2-209 on Tuesdays 2-3pm. Students will be selected to present an informal discussion of a chosen paper. Credit (pass/fail only) for the seminar is given based on your participation.
Participants
Fall 2008
| Date
|
Presenter
|
Paper
|
| 9/30/08
|
Jeff
|
Jaydeep P. Kulkarni (Purdue Univ.), Keejong Kim (Broadcom Inc.), Sang Phill Prak (Purdue Univ.), Kaushik Roy (Purdue Univ.), Process Variation Tolerant SRAM Array for Ultra Low Voltage Applications, DAC2008.
|
|
| 9/30/08
|
Keven
|
Jie Yang (University of Michigan), Luigi Capodieci (Advanced Micro Devices), Dennis Sylvester (University of Michigan), Advanced timing analysis based on post-OPC extraction of critical dimensions, DAC2005.
|
| 10/7/08
|
Seokjoong
|
Seungwhun Paik, Youngsoo Shin (KAIST), Multiobjective Optimization of Sleep Vector for Zigzag Power-Gated Circuits in Standard Cell Elements, DAC2008.
|
| 10/7/08
|
Everyone
|
5 Minute Update
|
| 10/14/08
|
Xuchu
|
Minsik Cho, Suhail Ahmed, David Z.Pan, TACO: Temperature Aware Clock-tree Optimization DAC2005
|
| 10/14/08
|
Derek
|
Gupta, M, Oatley, J, Joseph, R, Gu-Yeon Wei, Brooks, D, Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network DATE2007
|
| 10/21/08
|
Sheldon
|
Wei Huang, Micrea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando,Kevin Skadron, Many-Core Design from a Thermal Perspective DAC 2008
|
| 10/21/08
|
Everyone
|
5 Minute Update
|
| 10/28/08
|
|
No Class
|
| 11/04/08
|
Xuchu
|
A. Chakraborty,K. Duraisami,A. Sathanur,P. Sithambaram,L. Benini,A. Macii,E. Macii,M. Poncino , Dynamic thermal clock skew compensation using tunable delay buffers ACM2006
|
| 11/04/08
|
Keven
|
Tai-Chen Chen,Guang-Wan Liao,Yao-Wen Chang Predictive Formulae for OPC with Applications to Lithography-Friendly Routing
|
| 11/11/08
|
|
Veteran's Day (No Class)
|
| 11/18/08
|
Jeff
|
1Rajiv Joshi, 2Rouwaida Kanj, 1Keunwoo Kim, 3Richard Williams, and 1Ching-Te Chuang, 1IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, 2IBM Austin Research Labs, Austin Tx 78758, 3IBM STG, Essex Junction, VT 05452, rvjoshi@us.ibm.com, A floating-body dynamic supply boosting technique for low-voltage ...], DAC2006.
|
| 11/18/08
|
Everyone
|
5 Minute Update
|
| 11/25/08
|
Seokjoong
|
Yu-Shiang Lin; Sylvester, D., Runtime leakage power estimation technique for combinational circuits, ASP-DAC 2007.
|
|
| 11/25/08
|
|
|
| 12/02/08
|
Sheldon
|
Practice qualification talk.
|
| 12/02/08
|
Everyone
|
5 Minute Update
|
Potential Papers
Old Schedules
Spring 2008
| Date
|
Presenter
|
Paper
|
| 4/7/08
|
Rigo
|
S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning Through Better Local Search" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333.
|
| 4/7/08
|
Sheldon
|
Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD, 2003, pp 689-697
|
| 4/14/08
|
|
No class (@ ISPD)
|
| 4/21/08
|
Matt
|
Satisfiability (No Paper)
|
| 4/28/08
|
Derek
|
Verilog-A & Current Work
|
| 5/5/08
|
-
|
Out of Town
|
| 5/12/08
|
Jeff
|
B. Mohammad, M. Saint-Laurent, P. Bassett, and J. Abraham. Cache Design for Low Power and High Yield. ISQED, 2008, pp 103-107.
|
| 5/19/08
|
Keven
|
J. Sheaeffer D. Luebke K. Skadron A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors. ACM, 2007
|
| 5/26/08
|
Nobody
|
No class (Memorial Day)
|
| 6/2/08
|
-
|
No Class
|
|
| 6/9/08
|
-
|
No Class (@ DAC)
|
Winter 2008
| Date
|
Presenter
|
Paper
|
| 1/10/08
|
-
|
NOT MEETING
|
| 1/17/08
|
Matt
|
M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS.
|
| 1/24/08
|
-
|
NOT MEETING
|
| 1/31/08
|
Yaron
|
Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
|
| 1/31/08
|
Rigo
|
F. Wang, X. Wu and Y. Xie, Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning, ASPDAC 2008.
|
| 2/07/08
|
-
|
NOT MEETING
|
| 2/14/08
|
Sheldon
|
Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003.
|
| 2/14/08
|
Keven
|
K.-C. Wu and D. Marculescu, Soft Error Rate Reduction Using Redundancy Addition and Removal , ASPDAC 2008.
|
| 2/21/08
|
Jeff
|
Liang, X., Turgay, K., and Brooks, D. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD, 2007, pp 824-830.
|
| 2/21/08
|
Jeff
|
Cacti
|
| 2/28/08
|
Mohammed
|
Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.
|
| 2/28/08
|
Linh
|
Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD 2007, pp 450-457.
|
| 3/6/08
|
|
NO MEETING
|
| 3/13/08
|
Janak H. Patel (UIUC)
|
CMOS Process Variations: A "Critical Operation Point" hypothesis
|
