RAMP Relation

RAMP is a collaborative research community that aims at using FPGAs to accelerate processor simulations. Most RAMP projects aim at multiprocessor acceleration.

This is a similar goal to SCOORE, a major difference is that RAMP does not have an emphasis on ASIC or synthesis but rather on the FPGA acceleration.

RAMP common interface divides the RTL implementation in 3 blocks:

-Model RTL: The RTL required to implement a CPU/Memory/... model. Equivalen to the synos/scoore directory.

-Unmodel RTL: The RTL required to gather statistics or control the modeled architecture. It may not be necessary to execute instructions in the model architecture, but it is a requirement for researchers.

-Platform RTL: Each model and unmodel RTL needs to be synthesized in a specific FPGA platform. The platform RTL is the RTL specific for each platform.

The RAMP project aims at providing a common interface to avoid platform and unmodel RTL. SCOORE can benefit as it could potentially reuse both.