RAMP Relation

RAMP is a collaborative research community that aims at using FPGAs to accelerate processor simulations. Most RAMP projects aim at multiprocessor acceleration.

This is a similar goal to SCOORE, a major difference is that RAMP does not have an emphasis on ASIC or synthesis but rather on the FPGA acceleration.

RTL Layers

RAMP common interface divides the RTL implementation in 3 blocks:

-Model RTL: The RTL required to implement a CPU/Memory/... model. Equivalen to the synos/scoore directory.

-Unmodel RTL: The RTL required to gather statistics or control the modeled architecture. It may not be necessary to execute instructions in the model architecture, but it is a requirement for researchers.

-Platform RTL: Each model and unmodel RTL needs to be synthesized in a specific FPGA platform. The platform RTL is the RTL specific for each platform.

The RAMP project aims at providing a common interface to avoid platform and unmodel RTL. SCOORE can benefit as it could potentially reuse both.

Unit / Channel

RAMP partitions the design into units and channels. Main characteristics:

-Units only communicate through channels -Units wait until all the inputs (in channels) are ready before generating outputs (out channels) -Channels have a fixed latency -Channels are unidirectional -Channels have an initialization -A firing happens when a unit reads/consumes all the inputs and generates all the outputs.

The RAMP channels are similar to the SCOORE inter-block communication. In SCOORE:

-All the inputs are read every cycle. The unit or block is responsible to read. A key difference is that in SCOORE we can set a "busy" signal which means that the following cycle the sent packet would not be processed until the busy is deasserted

-RAMP uses a "enable" signal to notify that the channel has data. We use a "valid" signal. E.g:

 typedef struct packed{
   BoolType                            valid;
   BoolType                            fault;
   RIDType                             RID;
   OPType                              op;
   PRegType                            psrc1;
   PRegType                            psrc2;
   IMMType                             imm;
   PRegType                            pdest;
 }DInst_SEType;