Simulating Verilog

From Vlsiwiki
Revision as of 16:35, 28 January 2008 by 128.114.59.176 (Talk)

Jump to: navigation, search

Introduction

This section will briefly talk about how to simulate Verilog. You can simulate Verilog that is either behavioral, gate-level, or back-annotated (with delays). Behavioral and gate-level are done in the same way, but back annotate requires an extra system call in your Verilog.

Running Verilog

You can use two different Verilog simulators: ncverilog ("ncverilog") or verilog-XL ("verilog").

Simulating Verilog in Ultrasim

For non-digital simulations, you can simulate a structural Verilog netlist in Ultrasim as well. However, you need to supply the spice subcircuits of the library:

/mada/software/techfiles/osu_soc_v2.7/cadence/lib/tsmc025/signalstorm/osu025_stdcells.sp


Back-Annotation

In order to back-annotate, you should output an SDF file from either Synopsys Design Compiler (before physical design) or from SoC encounter. Each SDF format is sometimes different, so you may have to hack it to get it to work. Common incompatibilities are the dilimiting characters in hierarchical names, for example. Carefully watch the warnings!

The system call to back-annotate is like this:

initial begin
  $sdf_annotate("gate/lfsr-final.sdf", l0);
end

where lfsr.sdf is the SDF file and l0 is the instance name of the top module that you synthesized. Note that you should not be using your unsynthesized verilog now. Use the output from synthesis in the file, gate/lfsr-final.v, along with your original testbench.